R. N. Mercer, M. Ebel, and R. F. DeMara,
"Pipelined Architecture for Computational Nanotechnology," in Proceedings of the
1994 IEEE Southcon Conference (Southcon'94), pp. 314 -319, Orlando, Florida,
U.S.A., March 29 - 31, 1994.
Abstract:
Nanomechanical computing elements which are scalable in terms of input size and
depth of the propagation path are analyzed using a bounded continuum model.
Boolean logic functions of NOT,AND,OR and XOR are realized using helical latch,
reset spring and translating rod assemblies.Building upon these components a
design for two-level logic operations is presented. The helical latch mechanism
calculates the Boolean output functions as a positional displacement from a
known reset state, which occurs exactly once during each instruction cycle. To
balance forces a symmetrical robot is uesd to conteract applied forces by
replicating input rods. This has the beneficial side-effect of providing
intrinsic fault-detection capability within a gate and also decrease the
rotation required for a full cycle from 360 degrees to 180 degrees.
This design is further enhanced to allow arbitrary word length by subdividing
the logic disc into sectors where each sector contains all the components
necessary to operate on a single bit. The benefits of increasing the disc
diameter needed for additional bits include a further reduction disc cycle
rotation as a result of subdividing the disc into sectors. Since the inputs are
sampled sequentially, throughput of the resultants can be increased directly by
pipelining multiple bit operands. For n inputs per logic gate,the maximum
speedup for single level of logic is (n+2). Generally,the speedup is bounded by
(n+2)/p where p donates the number of cycles between initiations of the pipe.