S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb,
"Optimization of NULL Convention Self-timed Circuits,"
Integration, The VLSI Journal, Vol. 37, No. 3, August, 2004, pp. 135 - 165.
Abstract:
Self-timed logic design methods are developed using Threshold Combinational
Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic
functions are realized using 27 distinct transistor networks implementing the
set of all functions of four or fewer variables, thus facilitating a variety of
gatelevel optimizations. TCR optimizations are formalized for NCL and then
assessed by comparing levels of gate delays, gate counts, transistor counts, and
power utilization of the resulting designs. The methods are illustrated to
produce (1) fundamental logic functions that are 2.2-2.3 times faster and
require 40-45% fewer transistors than conventional canonical designs, (2) a Full
Adder with reduced critical path delay and transistor count over various
alternative gate-level synthesis approaches, resulting in a circuit with at
least 48% fewer transistors, half as many gate delays to generate the carry
output, and the same number of gate delays to generate the sum output, as its
nearest competitors, and (3) time, space, and power optimized increment circuits
for a 4-bit up-counter, resulting in a throughput-optimized design that is 14%
and 82% faster than area- and power-optimized designs, respectively, an area-
optimized design that requires 22% and 42% fewer transistors than the speed- and
power-optimized designs, respectively, and a power-optimized design that
dissipates 63% and 42% less power than the speed- and area-optimized designs,
respectively. Results demonstrate support for a variety of optimizations
utilizing conventional Boolean minimization followed by table-driven gate
substitutions, providing for an NCL design method that is readily automatable.