Department of Electrical Engineering & Computer Science


EEL 3801 Reports

  • Fall 2016:

  • Topic: Emerging Arithmetic Logic Units and Trade-off Analysis
    - A Breakdown and Comparison of Various Metrics for Different ALU Architectures and Technologies
    - A comparison of new technologies and design techniques to reduce power dissipation and decrease execution time
    - A Comparison of Technology Scaling Over a 16 Year Period with Innovative Technology Devices
    - A Comparison of Time and Power Dissipation Metrics for Adder Operations in CMOS Technology V.S. Emerging Alternate Logic Gate Technology
    - A Comprehensive Comparison of ALU or Floating Point Unit Architecture and Device Technologies
    - A look at various ALU and FPU designs and a comparison of node size bus width energy consumption and delay
    - A Need for Speed with Reduced Power-An ideological look at how ALUs have Improved Over Time
    - A review of research studies done using Full-Adders over the course of a decade
    - A Study of The Advancement of CMOS ALU & Full Adder Circuit Design For Modern Design
    - A Survey of ALU Designs from 2005 to 2016
    - Adder Designs and Effects on Power Consumption Processing Speed and Size Constraints
    - ALU and FIR design including Floating Point Analysis in CMOS technology Between the Years 2002-2015
    - ALU Design-Improvement Over Time Analysis
    - An Analysis and Metrics of Various ALU Adder Technologies by Year Performance Space and Power Consumption
    - An Analysis of Datapath Width Execution Time Technology Size and Power Consumption Between Adders, ALUs , and Floating Point Units
    - An Analysis of Full Adders and Floating Point Units- Optimization using beyond CMOS Technology
    - An analysis of new CMOs adder designs to improve ALU energy consumption
    - An analysis of performance of Adders-the tradeoff between execution time and energy efficiency
    - An Analytic Comparison of CNFET design and MOSFET design in CMOS through Time
    - An Analytical Review of Several Designs Which Employ FPGA, CMOS, DWNM, and CNFET Technologies, with Ranging ITRS nodes, and Varying Power Consumption
    - Analysis of Adder Multiplier Floating Point designs and their Metrics for better Performance and Efficiency
    - Analysis of ALU and Floating Point designs for Delay, Area and Power Efficiency
    - Analysis of ALU and Floating-Point Designs Power Size and Speed For the Growing Technological Use Since the Year 2000
    - Analysis of ALU design in CMOS technology
    - Analysis of ALU Designs from 2002-2016 and Their Tradeoffs based on Execution Time, Power Consumption, and Node Size
    - Analysis of ALU Designs’ Aim for Improvement in Processor Efficiency and Capability from 2001-2016
    - Analysis of ALU Trends Based on Design Performance and Year Setting
    - Analysis of Design Trade-offs of Arithmetic Logic Units from 2002-2015
    - Analysis of device technologies focusing on energy consumption and technology size through time
    - Analysis of Different ALU Devices and the Measurements That Accompany Them
    - Analysis of Full Adders with Varying Device Technology and the Chronological Progression of Different Metrics for ALUs
    - Analysis of Logical Unit Power Factors from a Circuit Perspective
    - Analysis of metrics for different ALU technologies
    - Analysis of Various Device Architectures and Their Trends Over The Years
    - Analysis of Various Technological Advances Throughout the Past Twenty Years
    - Analytical Comparison of Full-Adder Design Characteristics from the Years 2002 to 2016
    - Analyzing and Comparing ALU Design, Construction, and Performance Over Time Through Observed Metrics
    - Analyzing the Various Benefits Found Through the Study of CMOS, N-well, CNFET, and Domain Wall Nanomagnet Technology
    - Arithmetic Design Metrics on Area and Time efficiency of CMOS and Spintronic Devices
    - Arithmetic Logic Unit – Adder Functionality and Performance Regarding Operation Time and Energy Consumption
    - Arithmetic logic Unit Designs using Different Device Technology and Technology nodes
    - Assessment of Arithmetic Logic Unit and Power Density per Area Evolution from 2002-2015
    - CMOS Adders Development and Implementation Overtime
    - Comparing Arithmetic Logic Unit Performance, Design, and Capabilities of technologies from the recent decade
    - Comparing Full Adder Designs to support Moore’s Law and compare CMOS designs to newer technology
    - Comparing Operation Time of ITRS Technologies with Low Power Usage
    - Comparing the Energy Efficiency of Eight Different CMOS Full Adder Designs Built In the Last 15 Years
    - Comparison and Analysis of ALU and Floating Point Designs Throughout the Years 2003 and 2016
    - Comparison of ALU Designs with Same Device Technology but Different Design Approaches
    - Comparison of different device technologies from 2002-2016 and an estimate towards where future technology is moving
    - Comparison of Full Adders Designed Utilizing Traditional CMOS Technology vs. Various Non Traditional Technologies and Their Effects on Energy Consumption Performance
    - Comparison of Improvements, Augmentations, and Possible Alternatives for CMOS Based Integrated Circuits
    - Comparison of Operation Time and Power Usage for Present Technologies Relative to Technologies from 2014 to Present
    - Comparison of Various Metrics and Technologies Utilized in Assorted Arithmetic Designs
    - Computer Organization Capstone-Computer Architecture and Their Device Technology
    - Developing Needs of Computing Supersede Full Adder Performance Metrics
    - Different Perspectives within ALU Designs and their Tradeoffs
    - Effect of transistor size on power dissipated and delay of multiple ALUs
    - EFFICIENCY FOR CMOS TECHNLOGY OF ALU AND FLOATING POINT DESIGN ANALYSIS
    - Emerging Device Technology and opt for Architectural designs from 2000-2016
    - Energy Consumption and Performance of Energy Efficient and High Speed Full Adders
    - Energy Efficiencies Trends of ALU and Floating Point Architecture from 2001 to 2016
    - Evaluating Data Bus Width ITRS Technology Energy Consumption and Time for Operation per Year for Arithmetic Designs Between 2002-2016
    - Exploring Techniques for Reduction of Power Consumption in ALU Circuits
    - Extrapolation and Explanation of Power, Delay and Area Trade-offs in CMOS-based Arithmetic Logic Units (ALU)
    - Finding a Compromise Between Speed, Size, and Energy Efficiency in ALU Full Adders
    - High Performance ALUs Increase Design Complexity and Performance while Maximizing Power Consumption
    - High-Level Energy, Size, and Performance Comparison of Various Novel Arithmetic Designs between 2003 and 2015
    - Improved Aspects of 8 ALU Designs Since 2002
    - In Depth Analysis of the Progression of Full Adder Devices Over Time
    - In-Depth Review of ALU or Floating Point Computer System Metrics
    - Inventive enhancement and development of selected essential metrics pertaining to the topics of ALU and Floating Point Unit design
    - Investigation of 8 Arithmetic Logic Unit Full Adder Designs Performances and Technologies Employed Between 2000 and 2015
    - Metrics Analysis of ALU Designs From 2002 to Present Day
    - Objective and Subjective Analysis of ALU Designs Using Several Unique Device Technologies
    - Progression of Performance in Relation to Technology Node from 2002 - 2015
    - Research Analysis of Proposed ALU Designs to Compare Power Consumption Delay ITRS Technology Node Length and Area
    - Sacrifice of Power Consumption and Execution Time versus Size Analysis of Full Adder Designs from 2005 - 2016
    - Study of ITRS Tech Node Size Execution Time and Power Consumption from 2000-2016
    - Survey of Techniques for Continuing Improvement of Fundamental Computing Hardware
    - Technology Evolution Through Pipelining and Clock Gating Techniques
    - The Advancement and Balance of Various ALU Designs in Speed, Size, and Power Efficiency from Years 2003-2015
    - The Advancement of ALU’s, Full Adders, and Floating-Point Units throughout the 2000’s
    - The Comparison and Trends of the Multiples ALU Designs throughout the Years 2005 to 2016
    - The improvement in CMOS technology over the course of thirteen years (2003-2016)
    - Time Eclipsing Changes of the CMOS and Other Device Technologies in ALU and Full Adder Devices
    - Trade-off analysis and Technological Comparisons Between Different IEEE Format Style Reports

  • Summer 2016:

  • Topic: Emerging Memory Technologies Specifications and Trade-off Analysis
    - Trade Offs of Varying Cache Compositions Between 2006 and 2016 Based on Energy Leakage and Write Latency
    - Cache Configuration Trend between STT-RAM and eDRAM/SRAM Technologies from the Last Five Years
    - A Brief Compendium of On Chip Memory Highlighting the Tradeoffs Implementing SRAM, STT-RAM, or eDRAM
    - Cache Memory Introduction and Analysis of Performance Amongst SRAM and STT-RAM from The Past Decade
    - Improvement in Performance of Cache Processes with Advancing Hardware Technology
    - Upsides of Using STT-RAM: Detailed Comparison of Energy Consumption and Cache Latency for 4MB SRAM/eDRAM and 4MB STT-RAM Designs
    - Analysis of Multilevel Cache Configuration Performance and Design Trends over the Past Decade
    - Comparisons Of Different Level Of Cache Using Various Technologies From Multiple Reverences
    - Cache Configuration Analysis with emphasis on STT-RAM and emerging RAM Technologies
    - STT-RAM, SRAM, BRAM, ReRAM, and eDRAM Analysis of Their Advantages and Disadvantages
    - Analysis of the Fundamental Metrics of Processor and Cache Memory Over the Past Decade
    - Review of Multilevel Cache Memory and Their Energy Consumption Metrics
    - Investigation into the Specifics of the use of STT-RAM and SRAM in Cache Hierarchies
    - Technology and Performance Comparison of Cache Design and Memory
    - Compare The Metrics Between Different Types of Cache Memory from 2005-2016
    - STT-RAM vs. SRAM/eDRAM and Efficiency Analysis between Differing Cache Configurations
    - A Comparison of Energy Efficient Cache Design Architectures and Cache Scheme Techniques throughout the Past Decade
    - Comparing Cache Hierarchies and Advancement in Device Technologies Throughout the 2010’s
    - An insight into modern cache systems utilizing SRAM, eDRAM, and STT-RAM
    - A Comparison of Ten Different Memory Designs and Their Metrics Covering a Span of 21 Years
    - Detailed Analysis on the Dynamic World of Cache Configuration
    - Analysis on Cache Configuration Trends and Discrepancies throughout the Past Years: 2006-2016
    - Comparison of Energy and Performance Efficiency of Recent Cache Configuration Trends and Designs
    - Identification of CPU Latency and Energy Consumption Across Various Publications
    - Comparison of SRAM and STT-RAM Cache Configurations in Areas of Energy Consumption and Cache Latency
    - A Review of STT-RAM, SRAM, and eDRAM and Methods of Optimization for Computer Architecture
    - A Cache Comparison: Using Latency, Energy, Area, and IPC to Compare STT-RAM, SRAM, and eDRAM
    - Analysis of Cache Configurations and Cache Hierarchies Incorporating Various Device Technologies over the Years
    - Distinction of Modern Cache Configurations: SRAM, STT-RAM, and eDRAM Memory Performance Enhancement with Energy and Design Efficiency Analysis
    - Cache Configuration: The (Not-So) Hidden Importance and Evolution of Multilevel Caching
    - Understanding Unorthodox Cache Systems Designs by Comparing Their Different Metrics
    - Comparison of Different CPU Cache Technology Used in Testing for Research Purposes
    - Modern Improvement of Cache Latency and Energy Consumption Models in Device Technologies
    - Comparing Cache Latency and Energy Consumption Metrics in SRAM, eDRAM and STT-RAM Amongst Various Computer Architectures
    - Revolutionizing Technological Devices such as STT- RAM and their Multiple Implementation in the Cache Level Hierarchy
    - Important cache metrics from several CPUs observing different years, cores, and frequencies
    - The Improvements Of Cache Configurations
    - A Comparison of Efficiency Factors for SRAM and STT-RAM
    - Cache Configurations with Advancements in STT-RAM and Cache Levels
    - Implementation of Cache Designs and Efficiency of Cache Memory
    - New Age Technology Hierarchy SST-RAM and Multi Cache Duality Data trade-offs
    - Cache Memory Configurations and Their Respective Energy Consumption
    - Performance Metric of SRAM and STT-RAM Cache Level2
    - The effects of multilevel cache on CPU and main memory interactions
    - The effects of multilevel cache on CPU and main memory interactions
    - Energy Optimizations of SRAM and STT-RAM Multi-Level Caches from 1995-2016
    - Cache Memory: An insight on Cache Configuration and Cache Metrics
    - An Analysis of Cache Designs for Processors Used in Various Studies between 2006 and 2016
    - Memory-Hierarchy Configurations with Different Cache Technologies from 1995-2016
    - A Look into Cache Configuration and Device Technology Designs
    - Comparing New and Old Designs of Cache to Better Understand Latency
    - Meta-Comparison of SRAM, eDRAM, and STT-RAM in Terms of Latency and Energy Consumption
    - Cache Hierarchy Analysis and Performance - A study of efficient cache configurations using STT-RAM/eDRAM(2011-2016)
    - An Analysis of Cache Configurations Comparing SRAM, STT-RAM, and DRAM for Size, Performance (Hit Rate), and Energy Efficiency Between 1996 – 2016
    - An Analysis of Changing Trends within Various Metrics of Multilevel Cache Designs
    - Multi-level Cache Design and Improvement in Latency and Energy Consumption from 2000-2016
    - Review of different memory metrics with a particular focus on contrasting SRAM and STT-RAM
    - STT-RAM, SRAM, eDRAM: An Analysis of Metrics for Multilevel Cache Memory Technology
    - Device Technology and Cache Associativity of Various Cache Configurations

  • Fall 2015:

  • Topic: Real-World Processor Specifications and Trade-off Analysis
    - Analysis of Data Bus Width Affecting Power Efficiency and ITRS Node Technology over the past decade
    - Analysis of ALU and FPU Design Trends For Increasing Processor Efficiency from 2002-2015
    - ALU Design and Philosophy Trends and Progression in Research from 2000-2015
    - Advances Power Efficiency of an Arithmetic Logic Unit through Size and Design
    - A Survey of Experimental ALU Designs Indicating Trends in Energy Efficiency over 1999 to Present.
    - Optimized ALU Designs Advancing Time and Space Complexities
    - Systematic Analysis of Various Arithmetic Logic Units and Processors over the Last Two Decades
    - The Relationship between ITRS Technology Node Size and Energy Used by the Central Processing Unit (CPU)
    - Floating point and Arithmetic Logic Units analyzed on Power and Energy Consumption in Microprocessors
    - ALU Design using Various Approaches for Minimizing Energy Consumption from 2002-Present
    - Comparison of the different Data-path size of 10 designs for adders, multipliers, and floating points.
    - Comparing the Power and Energy Dissipations of Different Techniques On different models of FPGA Boards
    - An Analysis of ALU and Floating Point Unit Metrics and Designs Spanning Fifteen Years

    - Comparison in multiple timelines in implementing FPU and ALU designs to improve SPECs
    - Analysis of Implementation of ALU and FPU Operations and Size and the Effect on Power Dissipation, from 1999 to 2015
    - ALU and Floating Point Efficiency and Effectiveness in computing devices
    - Cost affective ALU designs that save energy with increased performance
    - Analyzing Different ALU Designs and Comparing Their Metrics Based on Year Spanning From 2002-2015
    - The Trend of Using Increasingly Specialized Data Bus Widths through the Years
    - Analysis of Multiple Low-Power ALU Designs Including Pipeline, FSL Logic, DFT scheme and Chain Structure Techniques
    - Looking at the Arithmetic Logic Unit and its Importance through the Years of 2002-2015
    - Evaluation of Energy Efficient Processors with a Minimized Area Design and Low Voltage Operation
    - Effects on Efficiency through Advancements in ALU Design-Trends and What to Expect for the Future
    - A Retrospective Examination of Moore's Law in Relation to Multiple ALU Designs from 2000 to Present Day
    - The development of the microprocessor involving the Arithmetic Logic Unit and the changes within the data bus, processor and power consumption
    - Clock Rates of CMOS based logic devices versus FPGA tested units
    - A Scientific Insight to Exemplary ALU's, Floating Point Designs, and Effective Processing Units
    - Comparing designs and metrics of ten different ALU architectures from 1999 to 2015
    - The Progression of Moore's Law in Relation to the Decrease of Power Consumption in ALUs
    - Fundamental ALU Metric Analysis of Proposed Designs and Applications in Years 2000-2015
    - Energy, Time, and Space Complexity Analysis of ALU Designs' Spanning from 2000 to the Present
    - A Multi-System analysis of ALU/FPU Complexity and Performance Relative to Time
    - Designer's Constant Quest to Reduce the ITRS Size and Power Consumption of the Processor
    - Innovating the ALU to Significantly Increase Performance from 1999 to 2015
    - The Trends of Energy consumption and Data Bus Width of 21st century processor designs
    - ALU Design: The Rapid Advancements of Computing Systems from 2000-2015
    - ALU and Floating Point Optimization using Multi-stage Pipelining and Clock Gating
    - A Comparison of Data Bus Width and Node Size of multiple generations of ALU/FPU designs and their relation to Moore's Law
    - Increasing Micro Device Technology Efficiency for ALUs and Plausible Solutions for Higher Performing Devices.
    - The Comparison of Different ALU Designs Versus the Year
    - An Analysis of energy efficient ALU Designs from the years 2000-2015
    - Lowering Power Dissipation and Energy Consumption in Arithmetic Logic Units From the Years 2002 to 2015
    - An Overview of Emerging Techniques and Trends in ALU Design through Comparison of Metrics From 1999 to 2015
    - An analysis of Arithmetic Logic Units Over the Past Decade
    - Techniques for ALU Advancements in Throughput, Space, and Efficiency in the New Millennium
    - Design and Power Consumption Analysis of Multiple ALU Structures
    - Various ALU and Floating Point Designs and Their Trends in Space, Time, and Energy Efficiency
    - Power Consumption and Dissipation As It Relates To ALU Design Over Time
    - Understanding ALU and ITRS technologies in many different ways
    - Consumer Driven Research Showing Advances in Moore's Law through CMOS Size, Power Dissipation, and Speed up
    - Comparison between the Energy Usage of Unique ALU Designs and Their ITRS Node Size
    - Analysis of power, operating frequency, efficiency, and operation time of ten ALUs from 1999 to 2015
    - Innovative improvement of fundamental metrics including power dissipation and efficiency of the ALU system
    - Explanation of Improved the Quality of ALU And Ten Different Types of Designs for Decreasing Power Dissipation
    - Comparison of Architecture Processors Focusing on ALU and Floating Point Unit Designs
    - Analysis of Metrics Used in ALU Design and Research as Related to Year of Publication of Academic Papers
    - ALU Energy Efficiency Analysis and the impact Calculation Complexity has on it
    - Differentiating views of lowering the energy use of ALU designs.
    - The Effect of Moore's Law: An Analysis of Arithmetic Logic and Floating Point Design Trade-offs
    - The Future of ALU Design to Increase Performance and Density While Reducing Power Consumption
    - Moore's Law: The Progression of the ALU and the ITRS Technology Node
    - An Analysis of Arithmetic Logic Unit Architecture Through The Years
    - Diverse Architectures for Low Energy High Throughput Computing
    - Analysis of Various High Speed Low Power Adder Compositions and Designs
    - A longitudinal study of Arithmetic logic unit and floating point unit performance, structure, and design
    - Analysis of Key ALU and Floating Point Metrics Spanning Between 2000 and 2015
    - Various Approaches to Utilize Power cuts and Produce high throughput from a Circuit.
    - Investigation of Multiple ALU Designs for Green Computing in the 21st Century
    - 21st Century ALU and FPU Design Analysis
    - ALU and Floating Point Architectures Metrics Analysis between 2003 and 2015
    - An Examination of the Resurgence of Low Powered Systems in the Early 21st Century
    - Comparison of Progressively Higher Energy Efficiency ALU Designs and Logic Techniques
    - Evaluation of ALU Design, Technology Size and Power Consumption from 2002-2015
    - Analysis of the Trends of Fundamental ALU Design Metrics Between the Years 2002 and 2015
    - Adder/Multiplier Design and Metric Evaluation
    - The Analysis of Thirteen Years of Low-Power ALU Designs Constrained to the Submicron Scale
    - Technology and Trends of Arithmetic Logic Units
    - ALU Designs for Power and Speed Optimization in the 21st Century
    - Analysis of ALU Power Savings through Different Designs and Approaches
    - - ALU and FPU Design Patterns Over The Last Decade
    - Consideration of the Last Fifteen Years of Advancements in ALU and Floating Point Designs and the Impact on Metrics Trade-offs.
    - Analysis of Various ALU Designs and Comparisons of Node Technology, Energy Use, and Performance from 2002-2015
    - The Configurations and Implementations of Different Adders and Multipliers in ALUs throughout the Past Decade
    - Power Consumption's Relationship to Word Width of Certain ALU Configuration Nodes Over the past Several Years
    - Quantitative Year to Year Differences Between 16 and 32-bit ALU Architectures
    - An Examination of Design and Optimization Decisions and Tradeoffs in Research and Development of New ALU and Floating Point Unit Design Over Recent Years
    - Analysis of Current Design Metrics Through Novel Quantization
    - ALU Floating Point Design: An Exploration of Advancement
    - Analyzing Metrics of ALU Designs Traversing from Years 2002 to 2015
    - Comparing Measurements in Various ALU Designs from 1999 to 2015
    - Techniques and Advancements of ALU Designs for Low Power Consumption.
    - The Metrics and Designs of an Arithmetic Logic Function over 2002-2015
    - Evaluation of ITRS technology node size reductions during the 21st century
    - An Analysis of Computer Systems and their relative performance using metrics to identify continuing trends and upcoming technology processes
    - Analysis of Temporal Localities regarding Efficiency and Implications on Moore's Law for Hardware Design Research
    - Analysis of Arithmetic Logic and Floating Point Unit Metrics Change in the Past 15 Years
    - Metric and Trend Analysis of Various Design and Logic Implementations
    - Where Technology has Led IEEE-754 Single Precision Floating Point Unit Devices, and Energy Efficient Multipliers

  • Summer 2015:

  • Topic: Processor Architecture Designs (1992-2011)
    - A look at Ten Processor Architecture from the 1990’s to the 21st Century
    - A Retrospective Examination of Moore’s Law Relative to Multiple CPU Designs from the 1990’s to Present Day
    - Advances in Processor Design and the Effects of Moores Law and Amdahls Law in Relation to Throughput Memory Capacity and Parallel Processing
    - A Review of Technological Trends as Shown in 10 Processors Through: Clock Rate, Memory, the Data Bus, and Multi-Core Designs
    - An Analysis of machine processors and their evolution of performance, metrics and intended uses with respect to time
    - Analysis of Processors Architecture and Increasing Capabilities of Processor Metrics
    - Analysis of Ten Computer System Designs with Respect to Clock Rate, Memory, number of Processors/Cores and Data Bus Width
    - Analysis of Trends of Fundamental Metrics in 10 Processors Developed from 1993 to 2011
    - Clock Rate, Memory Capacity, and Number of Processor’s Cores in the Evolution of Computer Architecture from the Early Nineties to the Present
    - Comparison of Processor Architectures and Metrics from 1992 to 2011
    - Comprehending the Von Neumann Architecture and the Diverse Ways It is Implemented Today
    - Computers Systems Over the Last 25 Years, Analyzing Moore’s Law to See if it Will Hold for Other Metrics
    - Determining the Relevancy of Moore's Law Through the Comparison of Ten Distinct Processor Systems
    - Evaluating and Comparing Selected Architecures to Measure the Fundamental Metrics of a Processor
    - Examining the Progression of Device Technology and the Implementation of Parallel Processing in Computer Systems
    - Exploration into the Measurements Used to Compare and Analysis Computer Systems
    - Fundamental Metrics of Processor Architectures from the 1990’s to the Present
    - Insight To Processor Architecture and Design Metrics, Analysis, and Comparison Between Ten Designs
    - Parallelism, Power consumption, Clock rate, and Voltage and their part in the progression of Processor Architectures
    - Processor architecture: Now and Then
    - Processors and Different Architectures: Comparison of Metrics 1990s to Present
    - Processors from 1990s to present
    - Review and Analysis of Select Performance Metrics for Processor Architecture Designs: a chronology from the 1990s to the Present
    - Survey of Processor Architectures and Applied Metrics
    - The Evolution of Processor Architecture through Hardware & Software Advances for Energy Optimization and Power Reduction through the 21st Century
    - The Relationship between Certain Metrics of a Processor and its Application
    - The Time is Moving and The Processor Technology also changing through time 1993 – 2014
    - Understanding unorthodox trends by comparing metrics of 10 processors; metrics include clock rate, memory capacity, word width, etc

    University of Central Florida