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Dr. Ronald F. DeMara

Pegasus Professor

Electrical and Computer Engineering
University of Central Florida

Director of the Computer Architecture Laboratory

 
ORCID ID: http://orcid.org/0000-0001-6864-7255

Concise Bio
Ronald F. DeMara is a Pegasus Professor in the ECE Department at the University of Central Florida, where he has been a full-time faculty member since 1993. He has completed over 325 articles, 50 funded projects as PI or Co-PI, and 57 graduates as Ph.D. dissertation and/or M.S. thesis advisor on topics of computer architecture with emphasis on emerging devices for machine learning, adaptive and reconfigurable hardware, and the digitization of STEM education. He has served ten terms as a Topical Editor or Associate Editor of various IEEE Transactions and technical conferences including General Co-Chair of GLSVLSI-2023. He has been a Keynote Speaker at IEEE iSES, IEEE IEMtronics, IEEE RAW, and IEEE ReConFig conferences. He is a Fellow of IEEE and AAAS. He has received the Joseph M. Biedenbach Outstanding Engineering Educator Award from IEEE.

 
Extended Bio
Ronald F. DeMara is Pegasus Professor in the Department of Electrical and Computer Engineering and joint faculty of Computer Science at the University of Central Florida, where he has been a full-time faculty member since 1993. His interests are in computer architecture, post-CMOS devices, and reconfigurable fabrics. He has applied these to autonomous, embedded, and intelligent/neuromorphic systems, on which he has completed over 325 articles, 50 funded projects as PI or Co-PI totaling $14.2M with one patent granted and one provisional patent, and 56 graduates as Ph.D. dissertation and/or M.S. thesis advisor. He was previously an Associate Engineer at IBM and a Visiting Research Scientist at NASA Ames, in total for four years, and is a registered Professional Engineer since 1992.        
His research has extended neuromorphic computing architectures using intrinsic stochastic post-CMOS devices; autonomous FPGA systems design at the register-level; soft error and BTI/TDDB resilient datapath design in deeply-scaled clocked CMOS; as well as clockless logic design and library development at the circuit-level; and dynamic runtime reconfiguration for energy/resiliency of signal processing fabrics at the system-level. He has completed projects on these topics sponsored by NSF, NASA, Army, Navy, Air Force, DARPA, NSA, SRC, and others. Additional recent work includes Field Programmable Analog Arrays, STT cache/LUT design, and neuromorphic functional elements/design flows of probabilistic spin logic devices. He teaches graduate and undergraduate courses on Computer Organization, Logic Design, Evolvable Hardware, and Emerging Device Computing Architectures.
     
He is a Senior Member of IEEE and currently serves as an Associate Editor of IEEE Transactions on Emerging Topics in Computing and was an IEEE Spectrum Editorial Advisory Board Member. He has completed ten terms as an Editor of various journals, including as Associate Editor of IEEE Transactions on Emerging Topics in Computing during 2019, as Senior/Topical Editor of IEEE Transactions on Computers in 2017-2018, as well as multiple terms as Associate Editor of IEEE Transactions on VLSI Systems and as an Associate Editor of IEEE Transactions on Computers. Additionally, he served on the editorial board of Microprocessors and Microsystems and the Journal of Circuits, Systems, and Computers. He oversaw as Topical Editor the IEEE Transactions on Computers Special Section on “Emerging Non-volatile Memory Technologies: from Devices to Architectures and Systems” in 2019. He was lead Guest Editor of IEEE Transactions on Emerging Topics in Computing joint with IEEE Transactions on Computers Special Sections on “Innovation in Reconfigurable Computing Fabrics from Devices to Architectures” in 2017. He was also a Guest Editor of ACM Transactions on Embedded Computing Systems Special Issue on Configuring Algorithms, Processes, and Architectures. He gave Keynote Addresses at the IEEE International IOT, Electronics, and Mechatronics Conference (IEEE IEMtronics) in 2020, 24th Annual IEEE Reconfigurable Architectures Workshop (IEEE RAW) conference in 2017, and IEEE International Reconfigurable Computing and FPGAs (IEEE ReConFig) conference in 2006.
     
Professor DeMara received best paper recognitions at the ACM Great Lakes Symposium on VLSI in 2018 and its best poster award in 2019, the International Symposium on Quality Electronic Design in 2017, and the IEEE-sponsored Adaptive Hardware and Systems conference in 2015, the International Conference on Field Programmable Logic, and others. He published a front-cover featured article in IEEE Computer magazine special issue on cognitive computing architectures in 2019 and the cover-page article in an IEEE Transactions on Magnetics regular issue during 2018, as well as a featured paper of the IEEE Transactions on Emerging Topics in Computing in 2019, a paper-of-the month in IEEE Transactions on Computers in 2017 and also in 2016, a featured article in IET Electronics Letters in 2016, and his IEEE Transactions on Circuits and Systems article was recognized for presentation at the IEEE International Symposium on Circuits and Systems in 2017.  He received the UCF Research Initiation Award (University-level) three times, Distinguished Research Lecturer Award (College of Engineering), the Advisor of the Year Award (College of Engineering), Excellence in Undergraduate Teaching Award (College-Level), Excellence in Graduate Teaching Award (ECE Department), twice received the Researcher of the Year Award (ECE Department), Teaching Initiative Award (College-level) five times, and the Scholarship of Teaching and Learning (SoTL) Award three times (University-level), Marchioli Collective Impact Award (University-level) for transformative impact, Excellence in Doctoral Mentoring Award (University-level), Pegasus Professor Award (‘University Professorship’ rank), and the Online Learning Consortium (formerly Sloan) Effective Practice Award, along with numerous best paper recognitions and IEEE Transactions of the Month. In 2023, he was General Co-Chair of IEEE/ACM Great Lakes Symposium of VLSI (GLSLVI-2023).
     
He was elected Fellow of American Association for Advancement of Science (AAAS) with citation: “For outstanding contributions in computer systems design and architecture with emphasis on emerging computing devices for machine learning, adaptive and reconfigurable hardware, and digitization of STEM education.” He was elevated to IEEE Fellow with citation: “for contributions to runtime reconfigurable computing and resilient datapath design.” He received the Joseph M. Biedenbach Outstanding Engineering Educator Award from IEEE.