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Recent Publications

  1. 26 Jan 2023: Our paper titled “Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator Framework”, has been accepted in IEEE International Symposium on Quality Electronic Design (ISQED).
  2. 20 Jan 2023: Our paper titled “Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy”, has been accepted in IEEE International Symposium of Circuits and Systems (ISCAS).
  3. 25 Sep 2022: Our paper titled “Scalable Reasoning and Sensing using Processing-in-Memory with Hybrid Spin/CMOS-based Analog/Digital Blocks,” has been accepted to IEEE Transactions on Emerging Topics in Computing (TETC): Thematic Section on Memory-centric Designs: Processing-in-Memory, In-memory Computing, and Near-memory Computing for Real World Applications.
  4. 14 Sep 2022: Our book chapter titled “MRAM-Based FPGA: A Survey,” submitted to the book under the working title “Field-Programmable Gate Arrays,” has been accepted for publication at Intechopen.
  5. 24 August 2022: Our paper “Energy-Efficient Recurrent Neural Network with MRAM-based Probabilistic Activation Functions” accepted to IEEE Transactions on Emerging Topics in Computing (TETC).
  6. 19 August 2022: Our paper “Utilization of Data Augmentation Techniques to Enhance Learning with Sparse Datasets” accepted to IEEE Conference on AI for Industry (AI4I).
  7. 16 July 2022: Our paper “Non-uniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation,” accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
  8. 20 July 2022: Our paper “Personalizing Digitized Assessments and Remediation using an Automated Micro-Credentialing Framework for Canvas LMS” accepted to OLC Accelerate 2022 Conference on Accelerating Online Learning Worldwide.
  9. 15 March 2022: Our paper  “The Impact on Learning Outcomes using Three-Attempt Tests in an Engineering Undergraduate Core Course: Dynamics,” accepted in Proceedings of American Society for Engineering Education (ASEE-SE-2022)
  10. 05 March 2022: Our paper “Rehosting YOLOv2 Framework for Reconfigurable Fabric-Based Acceleration,accepted to IEEE SoutheastCon 2022.
  11. 17 December 2021: Our paper “Generalized Exponentiation using STT Magnetic Tunnel Junctions: Circuit Design, Performance, and Application to Neural Network Gradient Decay,” accepted to Springer Nature Computer Science.
  12. 10 December 2021: Our paper “Spin-Orbit Torque Neuromorphic Fabrics for Low-Leakage Reconfigurable In-Memory Computation,” selected to Special Issue on Hardware for AI, Machine Learning, and Emerging Electronic Systems IEEE Transactions on Electron Devices (TED).
  13. 05 December 2021: Our paper “Algorithm and Hardware Co-Design Co-Optimization Framework for LSTM Accelerator using Fully Decomposed Tensor Train,” accepted to Work-in-Progress paper at ACM/IEEE Design Automation Conference (DAC).
  14. 01 November 2021: ”Digitally Mediated Team Learning: Foundational Perspectives – Book Shares on Designing Learning for Everyone,” Book Share Session Presentation at Association for Educational Communications and Technology, Chicago, IL, USA, published as hardcover book.
  15. 03 October 2021: Our paper “Non-uniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation,” accepted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
  16. 30 September 2021: Our paper “The Impact on Learning using Three-Attempt Tests in an Engineering Undergraduate Core Course: Dynamics,” accepted to 2022 American Society for Engineering Education Southeastern Conference.
  17. 30 September 2021: Our paper “Longitudinal Learning Outcomes from Engineering-Specific Adaptions of Hybrid Online Undergraduate Instruction,” accepted to International Journal of Emerging Technologies in Learning (iJET).
  18. 30 September 2021: Our paper “High Accuracy DBN-Fuzzy Neural Networks using MRAM-based Stochastic Neurons,” accepted to Special Topic on Emerging Hardware for Cognitive Computing, Special Issue in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (IEEE JxCDC). 
  19. 16 September 2021: Our paper “Embedded STT-MRAM Energy Analysis for Intermittent Applications using Mean Standby Duration,” accepted to IEEE International Conference on Electronics Circuits and Systems (ICECS-2021).
  20. 16 July 2021: Our paper “Long Short-Term Memory with Spin-Based Binary and Non-Binary Neurons,”  accepted to IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).
  21. 07 July 2021: Our paper titled “An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design,” accepted to IEEE International Conference on Application-specific Systems, Architectures and Processors (IEEE ASAP).
  22. 20 April 2021: Our paper “An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset,” accepted to IEEE Great Lakes Symposium on VLSI (GLSVLSI).
  23. 13 April 2021: Our paper “Process Variation Sensitivity of Spin Orbit Torque Perpendicular Nanomagnets in DBNs,” accepted to IEEE Transactions on Magnetics (TMAG).
  24. 29 March 2021: Our paper “A Reconfigurable and Compact Spin-based Analog Block for Generalizable nth Power and Root Computation,” accepted to IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2021).
  25. 16 February 2021: Our paper “Authenticated Testing during Blended Delivery: Impacts on Assessment Scores within an Engineering Undergraduate Core Course,” accepted to American Society for Engineering Education (ASEE-SE-2021).
  26. 02 February 2021: Our paper “Low-Energy Acceleration of Binarized Convolutional Neural Networks using a Spin Hall Effect based Logic-in-Memory Architecture,” accepted o IEEE Transactions on Emerging Topics in Computing (TETC).
  27. 16 February 2021: Our paper with lab alum Dr. Salehi now at UCD titled “Adaptive Non-Uniform Compressive Sensing using SOT-MRAM Multi-bit Precision Crossbar Arrays,” accepted to IEEE Transactions on Nanotechnology (TNANO).