@ARTICLE{4483522, 
author={Heng Tan and DeMara, R.F.}, 
journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, 
title={A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration}, 
year={2008}, 
month={May}, 
volume={16}, 
number={5}, 
pages={504-516}, 
keywords={application program interfaces;field programmable gate arrays;reconfigurable architectures;FPGA devices;PowerPC core;Xilinx Virtex II Pro platform;application programming interfaces;autonomous reconfiguration;autonomous run-time partial reconfiguration;benchmark algorithm;block RAM;field-programmable gate-array;field-programmable gate-array devices;hashing algorithm;logic control flow;multilayer run-time reconfiguration architecture;on-chip resources;reconfiguration layers;resource utilization;run time performance;Bitstream manipulation;FPGA run-time environments;field-programmable gate-array (FPGA) area management;frame-based partial reconfiguration;module-based partial reconfiguration}, 
doi={10.1109/TVLSI.2008.917551}, 
ISSN={1063-8210},}