Keywords: FPGA, Circuit Synthesis, Parallel Genetic
Algorithms, Evolvable Hardware, Multicore Computing

Abstract: Multicore processors are becoming common whereas current genetic algorithm-based implementation techniques for syn- thesizing Field Programmable Gate Array (FPGA) circuits do not fully exploit this hardware trend. Genetic Algorithm (GA) based techniques are known to optimize multiple objectives, and automate the process of digital circuit design. In this pa- per, parallel GA algorithms are proposed for the synthesis of digital circuits for LUT-based FPGA architectures. Parallel modes of the GA such as Master-Slave and the Island model are compared to see which scheme results in better speedup and quicker convergence for effective utilization of current multicore hardware. Speedup of about five over the sequen- tial single-threaded implementation is achieved with both the schemes on a six-core machine. Convergence is also found in fewer number of generations. The methods described here-in can be employed in Evolvable Hardware Systems as well as FPGA CAD tools.