S. E. Crawford and R. F. DeMara, 
"Cache Coherence in Multiport Memory Architecture," in Proceedings of the Second 
International Conference on Massively Parallel Computing Systems (MPCS'95), pp. 632 - 642, Ischia, Italy, May 2 - 6, 1995.

Abstract:
The effects of various cache coherence strategies are analyzed for a multiported shared-
memory multiprocessor. Analytical models for the Concurrent-Read-Exclusive-Write 
access(CREW) and Concurrent-Read-Concurrent-Write access (CRCW) are developed 
including shared-not-cacheable, snooping-bus,snooping-bus with cache-to-cache 
transfers, and directory protocols. The performance of each protocol is shown as the hit 
rate, main-memory-to-cache-memory cycle-time ratio, fraction of shared data,read 
percentage, and the number of partitions are varied.Overall, results indicate that a 
snooping-bus with cache-to-cache transfer scheme provides consistently fast access times 
over a wide range of execution parameters. However,nearly equivalent performance can 
be obtained with simpler directory-based schemes. The implications of these results on 
increasing ports complexity and memory usage are discussed.