R. F. DeMara, A. Kejriwal, and J. R. Seeber, 
"Feedback Techniques for Dual-Rail Self-Timed Circuits," in Proceedings of the 2004 
International Conference on VLSI (VLSI-04), pp. 458 - 464, Las Vegas, Nevada, U.S.A., 
June 21 - 24, 2004.

Abstract:
Design techniques for time and space optimization of NCL feedback circuits are 
developed and compared. First, a 3-Register Stage method is employed to circulate 
DATA and NULL wavefronts required to realize feedback in 4-bit binary timer case-
study. While modular and adaptable, this approach requires a significant gate count to 
realize the feedback circuit that comprises 75% of the total gates required. The second 
methodology aims at reducing the feedback overhead by using the state-maintaining 
capacity inherent with each threshold logic gate's built-in hysteresis behavior. This 
methodology employs two characteristics: the circuit preserves its present state; and it 
keeps track of the number of requests for DATA so that it can determine the appropriate 
next state. This embedded approach can reduce the feedback gate count by nearly 50% 
and also DATA-to-DATA cycle time by 31% depending on the feedback scheme used. 
Finally, the above-explained methodologies are assessed in terms of their design tradeoffs