J. Di, J. S. Yuan, and R. DeMara, "High Throughput Power-aware FIR Filter Design 
based on Fine-grain Pipeline Multipliers and Adders," in Proceedings of the 2003 
IEEE Annual Symposium on VLSI (ISVLSI'03), pp. 260 - 261, Tampa, Florida, U.S.A., 
February 20 - 21, 2003.

Abstract:
In regular FIR structure, by pipelining the multipliers one can improve the 
throughput. But as the growth of operand word length, the delay in addition 
process becomes another important constraint. In this paper, a novel fine-grain 
pipelining scheme for high throughput FIR is proposed. By pipelining multipliers 
and adders, very high throughput can be achieved. 2-Dimensional pipeline gating 
technique is used to make the designed FIR power aware to the precision of the 
operands. The average power dissipation and latency are both significantly 
reduced with changing of input precisions.