J. Huang, M. Parris, J. Lee, and R. F. DeMara, 
"Scalable FPGA Architecture for DCT Computation using Dynamic Partial Reconfiguration," in 
International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'08), 
Las Vegas, U.S.A., July 14-17, 2008.

Abstract:
In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial 
reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. 
This is important for some critical applications that need continuous hardware servicing. Our scalable 
architecture has two features. First, the architecture can perform DCT computations for eight different 
zones, i.e., from 1×1 DCT to 8×8 DCT. Second, the architecture can change the configuration of processing 
elements to trade off the precisions of DCT coefficients with computational complexity. Using dynamic partial 
reconfiguration with 2.1 MB bitstreams, 16 distinct hardware architectures can be implemented. We show the 
experimental results and comparisons between different configurations using both partial reconfiguration and 
non-partial reconfiguration process.