J. D. Lohn, G. Larchev, and R. F. DeMara, "Evolutionary Fault Recovery in a 
Virtex FPGA Using a Representation that Incorporates Routing," in Proceedings of 
the Seventieth International Parallel and Distributed Processing Symposium 
(IPDPS-2003) - Reconfigurable Architectures Workshop, pp. 172, Nice, France, 
April 22 - 26, 2003.

Abstract:
Most evolutionary approaches to fault recovery in FPGAs focus on evolving 
alternative logic configurations as opposed to evolving the intra-cell routing. 
Since the majority of transistors in a typical FPGA are dedicated to 
interconnect, nearly 80% according to one estimate, evolutionary fault recovery 
systems should benefit by accommodating routing. In this paper, we propose an 
evolutionary fault-recovery system employing a genetic representation that takes 
into account both logic and routing configurations. Experiments were run using a 
software model of the Xilinx Virtex FPGA. We report that using four Virtex 
combinational logic blocks, we were able to evolve a 100% accurate quadrature
Decoder. 


nite state machine in the presence of a stuck-at-zero fault. Evolutionary 
experiments with the
hardware in the loop have begun and we discuss the preliminary results.