Abstract—In this work we develop a novel way of handling
faults in a hardware design running on a reconfigurable platform.
At design time, we generate a diverse set of functionally identical
configurations utilizing alternate hardware resources in an FPGA
(Field Programmable Gate Array). As a part of the fault handling
methodology, these hardware-realizations are evaluated online
by actual inputs, and the pool is sorted using the PageRank
algorithm, currently utilized by the Internet indexing procedures.
We introduce CSG (Circuits Similarity Graph) in which entries
represent the similarity of the circuits. It is observed that the
configurations which use the faulty resources and hence manifest
faulty realization, receive lower rank. The most optimal configurations
in the dormant pool under the given fault conditions are
ranked higher by the PageRank algorithm, hence promoting them
appropriately. The results indicate that the method accurately
identifies the fault free configurations in a pool. We have used
post place-and-route simulation model for fault simulation which
most closely represents the actual model of the device. By not
interfering with vendor’s synthesizer and place-and-route tools,
the functionality of the design is always ensured.