S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, 
"Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction,"
in Proceedings of the 2001 International Workshop on Logic and Synthesis 
(IWLS'01), Granlibakken, California, U.S.A., pp. 185 - 189, June 12 - 15, 2001.

Abstract:
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput 
of delay-insensitive digital systems. NCR reduces the time required to flush 
complete DATA wavefronts, commonly referred to as the NULL or Empty cycle. The 
NCR technique exploits parallelism by partitioning input wavefronts such that 
one circuit processes a DATA wavefront, while its duplicate processes a NULL 
wavefront. To illustrate the technique, NCR is applied to a case study of a 
dual-rail non-pipelined 4-bit by 4-bit unsigned multiplier, yielding a speedup 
of 1.61 over the standalone version, while maintaining delay-insensitivity. NCR 
is also applied to a single slow stage of a pipeline to boost the pipeline?¡¥s 
overall throughput by 21%.