N. Weng, J. S. Yuan, R. F. DeMara, D. Ferguson, and M. Hagedorn, "Glitch Power 
Reduction for Low Power IC Design," in Proceedings of the Ninth Annual NASA 
Symposium on VLSI Design, pp. 7.5.1 - 7.5.7, Albuquerque, New Mexico, U.S.A., 
November 8 - 9, 2000.

Abstract:
Glitch power of a NCL multiplier is studied. The hysteresis threshold gates 
eliminate spurious power glithces significantly. The supply voltage signal 
bounce of the NCL circuit is also reduce drastically compared to its Boolean 
counterpart.