A Taxonomy of High Performance Computer Architectures for Uniform Treatment of Multiprocessor Designs

Abstract 

Seven distinct configurations of shared-memory multiprocessors are defined and parameterized in terms of the number of independent interface ports to the global shared data (P), the number of ports per memory device (D), and the number of ports supporting independent read accesses (R) and write accesses (W). The class of B-symmetric architectures containing N processors exhibit port utilization proportional to the quantity N/P and require physical memory capacity of size M, where M denotes the address range of the global shared-memory space. This class includes include the Single-Port through N-Port memory strategies. The class of U-symmetric architectures includes the Allocated Dual-Port, the Concurrent Read Replicated, and the Read-Time Resolution Coherent memory strategies. U-symmetric architectures decrease port contention by supporting up to R+W concurrent memory transactions per cycle. However, they require physical memory capacities ranging from N×M up to M×N2. This taxonomy has been useful in conceptualizing a large number of machine designs in terms of a unified model requiring relatively few independent parameters. This enables incremental understanding of multiprocessor architectures by progressing through different architectural classifications in a pre-defined sequence of increasing complexity.