Heng Tan,R. F. DeMara, “A Multi-layer Framework Supporting 
Autonomous Runtime Partial Reconfiguration,” accepted by IEEE 
Transactions on Very Large Scale Integration (VLSI) Systems 
on 17 July 2007. 


Abstract- A Multilayer Runtime Reconfiguration Architecture (MRRA) is developed for 
Autonomous Runtime Partial Reconfiguration of Field Programmable Gate Array (FPGA) devices.  
MRRA operations are partitioned into Logic, Translation, and Reconfiguration layers 
along with a standardized set of Application Programming Interfaces (APIs).  At each level, 
resource details are encapsulated and managed for efficiency and portability during operation.
In particular, FPGA configurations can be manipulated at runtime using on-chip resources.  
A corresponding logic control flow is developed for a prototype MRRA system on a Xilinx Virtex 
II Pro platform.  The Virtex II Pro on-chip PowerPC core and block RAM are employed to
 manage control operations while multiple physical interfaces establish and supplement autonomous
 reconfiguration capabilities.  Evaluations of these prototypes on a number of benchmark and hashing 
algorithm case studies indicate the enhanced resource utilization and run-time performance of the 
developed approaches. 

Index Terms¡ª FPGA Runtime Environments,
Module-Based Partial Reconfiguration, Frame-Based Partial 
Reconfiguration, FPGA Area Management, Bitstream Manipulation