Jian Huang, Matthew Parris, Jooheung Lee, and Ronald F. DeMara
University of Central Florida
"Scalable FPGA-based Architecture for DCT Computation Using Dynamic Partial Reconfiguration"
accepted to ACM Transactions on Embedded Computing Systems

In this paper, we propose FPGA-based scalable architecture for DCT computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has three features. First, the architecture can perform DCT computations for eight different zones, i.e., from 1 X 1 DCT to 8 X 8 DCT. Second, the architecture can change the configuration of processing elements to trade off the precisions of DCT coe±cients with computational complexity. Third, unused PEs for DCT can be used for motion estimation computations. Using dynamic partial reconfiguration with 2.3 MB bitstreams, 80 distinct hardware architectures can be implemented. We show the experimental results and comparisons between different configurations using both partial reconfiguration and non-partial reconfigurationprocess. The detailed trade-offs among visual quality, power consumption, processing clock cycles, and reconfiguration overhead are analyzed in the paper.
Categories and Subject Descriptors: B.6.1 [Logic Design]: Design Style
General Terms: Design, Experimentation
Additional Key Words and Phrases: FPGA, Dynamic Partial Reconfiguration, DCT, ME, scalability