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Journals

  1. Mohammed Essa, Peyton Chandarana, Ramtin Mohammadizand, and Ronald DeMara, “MRAM-Based FPGA: A Survey,” in Field-Programmable Gate Arrays, Vol. TBD, Intechopen, Sep. 2022, pp. BD-TBD. DOI: TBD.
  2. A. Tatulian and R. F. DeMara, “Non-uniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 41, No. 9, pp. 3157- 3161, Sep. 2022, DOI:10.1109/TCAD.2021.3119275.
  3. A. Tatulian and R. F. DeMara, “Generalized Exponentiation using STT Magnetic Tunnel Junctions: Circuit Design, Performance, and Application to Neural Network Gradient Decay,” selected to Special Issue on Hardware for AI, Machine Learning, and Emerging Electronic Systems in Springer Nature Computer Science, Vol. 9, No. 148, Jan. 2022. DOI: 10.1007/s42979-022-01039-7.
  4. M. Liu, P. Borulkar, M. Hossain, R. F. DeMara, and Y. Bai, “Spin-Orbit Torque Neuromorphic Fabrics for Low-Leakage Reconfigurable In-Memory Computation,” Selected to Special Issue on Hardware for AI, Machine Learning, and Emerging Electronic Systems, IEEE Transactions on Electron Devices, Vol. 69, No. 4, pp. 1727-1735, Jan 2022. DOI: 10.1109/TED.2021.3140040
  5. H. Pourmeidani* and R. F. DeMara+, “High Accuracy DBN-Fuzzy Neural Networks using MRAM-based Stochastic Neurons,” selected to Special Issue on IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), Vol. 7, No. 2, pp. 125 – 131, December 2021. DOI: 10.1109/JXCDC.2021.3117489
  6. R. F. DeMara, T. Tian, and W. Howard, “Longitudinal Learning Outcomes from Engineering-Specific Adaptions of Hybrid Online Undergraduate Instruction,” International Journal of Emerging Technologies in Learning, Vol. 16, No. 23, November 2021. DOI: 10.3991/ijet.v16i23.17615.
  7. H. Pourmeidani, P. Debashis, Z. Chen, and R. F. DeMara, “Process Variation Sensitivity of Spin-Orbit Torque Perpendicular Nanomagnets in DBNs,” in IEEE Transactions on Magnetics, vol. 57, no. 7, pp. 1-8, July 2021, Art no. 3401508, DOI: 10.1109/TMAG.2021.3075391.
  8. Salehi, Soheil, and Ronald F. DeMara. “Adaptive non-uniform compressive sensing using SOT-MRAM multi-bit precision crossbar arrays,” in IEEE Transactions on Nanotechnology (TNANO), vol. 20, pp. 224-228, Feb. 2021.
  9. R. F. DeMara, D. Turgut, E. Nassiff, S. Bacanli, N. H. Bidoki, and J. Xu, “Data Mining of Assessments to Generate Learner Remediation Teams: Efficacy and Perceptions in an Undergraduate Engineering Pilot Offering,” Journal of Educational Technology Systems, Vol. 48 No. 4, pp. 464 – 492, April  2020. DOI:10.1177/0047239520901863.
  10. S. Sheikhfaal and R. F. DeMara, “Short-Term Long-Term Compute-In-Memory Architecture: A Hybrid Spin/CMOS Approach Supporting Intrinsic Consolidation and Online Learning,” Selected to Special Issue on Exploratory Devices and Circuits for Compute-in-Memory, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Vol. 6, No. 1, pp. 62 – 70, March 2020.
  11. H. Pourmeidani, S. Sheikhfaal, R. Zand, and R. F. DeMara, “Probabilistic Interpolation Recoder for Energy-Error-Product Efficient DBNs with p-bit Devices,” IEEE Transactions on Emerging Topics in Computing, Vol. 9, No. 4, pp. 2146-2157, January 2020, DOI:10.1109/TETC.2020.2965079.
  12. A. Roohi, S. Sheikhfaal, S. Angizi, D. Fan, and R. F. DeMara, “ApGAN: Approximate GAN for Robust Low Energy Learning from Imprecise Components,” IEEE Transactions on Computers, Vol. 69, No. 3, pp. 349 – 360, March 2020, DOI: 10.1109/TC.2019.2949042.
    [pdf]
  13. V. Ostwal, R. Zand, R. F. DeMara, and J. Appenzeller, “A Novel Compound Synapse using Probabilistic Spin-Orbit-Torque Switching for MTJ-Based Deep Neural Networks,” Selected to Special Issue on Spin-Orbit Coupling Effects for Advanced Logic and Memory in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Vol. 5, No. 2, pp. 182 – 187 , December 2019. DOI: 10.1109/JXCDC.2019.2956468.
  14. R. Zand and R. F. DeMara, “MRAM-Enhanced Low Power Reconfigurable Fabric with Multi-Level Variation Tolerance,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 66, No. 12, pp. 4662-4672. DOI: 10.1109/TCSI.2019.2932379.
  15. L. O. Campbell, S. Heller, and R. F. DeMara, “Implementing Student-Created Video in Engineering: An Active Learning Approach for Exam Preparedness,” International Journal of Engineering Pedagogy, Vol. 9, No. 4, pp. 63-75, 2019.
  16. A. Samiee, P. Borulkar, R. F. DeMara, P. Zhao, and Y. Bai, “Low-Energy Acceleration of Binarized Convolutional Neural Networks using a Spin Hall Effect based Logic-in-Memory Architecture,” IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 928-940, 1 April-June 2021, doi: 10.1109/TETC.2019.2915589.
  17. A. Roohi and R. F. DeMara, “PARC: A novel design methodology for power analysis resilient circuits using spintronics,” IEEE Transactions on Nanotechnology (IEEE TNANO), Vol. 18, No. 1, pp. 885-889, December 2019.
  18. A. Samiee, Y. Sun, R. F. DeMara, Y. Choi, and Y. Bai, “Energy Efficient Mobile Service Computing through Differential Spin-C-element: A Logic-in-Memory Asynchronous Computing Paradigm,” IEEE Access,
    Vol. 7, No. 1, pp. 55851 – 55860, December 2019. DOI: 10.1109/ACCESS.2019.2911098.
  19. S. D. Pyle, J. D. Sapp, and R. F. DeMara, “Leveraging Stochasticity for In-Situ Learning in Binarized Deep Neural Networks,” Computer (a.k.a. IEEE Computer Magazine),
    Vol. 52, No. 5, pp. 30-39, May 2019.Featured Article on the Front Cover of the Issue. Selected to Special Issue on Cognitive Computing Systems and Applications.
  20. S. D. Pyle, R. Zand, S. Sheikhfaal, and R. F. DeMara, “Subthreshold Spintronic Stochastic Spiking Neural Networks with Probabilistic Hebbian Plasticity and Homeostasis,IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Vol. 5, No. 1, pp. 43-51, June 2019, DOI: 10.1109/JXCDC.2019.2911046.
  21. Y. H. Chang, J. Hu, M. B. Tahoori, and R. F. DeMara, “Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-volatile Memory Technologies: from Devices to Architectures and Systems,” IEEE Transactions on Computers, Vol. 68, No. 8, pp. 1111-1113, August 2019. DOI: 10.1109/TC.2019.2923033.
    [pdf]
  22. A. Alzahrani and R. F. DeMara, “Leveraging Design Diversity to Counteract Process Variation: Theory, Method, and FPGA Toolchain to Increase Yield and Resilience In-situ,IET Computers & Digital Techniques,
    Vol. 13, No. 3, pp. 250-261, May 2019. DOI: 10.1049/iet-cdt.2018.5012.
  23. R. Zand, K. Y. Camsari, S. Datta, and R. F. DeMara, “”Composable Probabilistic Inference Networks using MRAM-based Stochastic Neurons,ACM Journal on Emerging Technologies in Computing Systems (JETC),
    Volume 15, Issue 2, April 2019, DOI: 10.1145/3304105.
  24. T. Tian and R. F. DeMara, and S. Gao, “Efficacy and Perceptions of Assessment Digitization within a Large-Enrollment Mechanical and Aerospace Engineering Course,Computer Applications in Engineering Education,
    Wiley Publishing, Vol. 27, Issue 2, pp. 419 – 429, March 2019.
  25. M. Alawad, Y. Bai, M. Lin, and R. F. DeMara, “Robust Large-Scale Convolution through Stochastic-Based Processing without Multipliers,IEEE Transactions on Emerging Topics in Computing,
    Vol. 7, No. 1, pp. 80–97, January –March 2019. 10.1109/TETC.2016.2601220.
  26. S. Salehi, N. Khoshavi, R. Zand, and R. F. DeMara, “Self-Organized Sub-bank SHE-MRAM-based LLC: an Energy-Efficient and Variation-Immune Read and Write Architecture,Integration, The VLSI Journal,
    Vol. 65, pp. 293 – 307, March 2019. https://doi.org/10.1016/j.vlsi.2018.03.001.
  27. R. F. DeMara, T. Tian, and W. Howard, “Engineering Assessment Strata: A Layered Approach to Evaluation Spanning Bloom’s Taxonomy of Learning,Education and Information Technologies,
    Springer Publishing, vol. 24, no. 2, pp.1147-1171, Oct. 2018.
  28. F. Alghareb, R. Zand, and R. F. DeMara, “Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience,IEEE Transactions on Magnetics,
    Vol. 55, No. 3, pp. 1–11, March 2019.
  29. R. F. DeMara, S. Sheikhfaal, P. J. Wilder, B. Chen, and R. Hartshorne, “BLUESHIFT: Rebalancing Engineering Engagement, Integrity, and Learning Outcomes across an Electronically-Enabled Remediation Hierarchy,ASEE Computers in Education Journal, Vol. 10, No. 1, pp. 1 – 12, March 2019.
  30. R. F. DeMara, S. Salehi, R. Hartshorne, B. Chen, and E. Saqr, “Observable, Traceable, Autograded Computer-Mediated Collaborative Learning: A Pilot of Scalable Team Design in the Engineering Classroom,” Journal of Interactive Learning Research, Vol. 30, No. 2, 2019.
  31. N. Khoshavi and R. F. DeMara, “Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization,IEEE Access, Vol. 6, No. 1, pp. 14576 – 14590, December, 2018.
  32. S. Salehi and R. F. DeMara, “SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter Leveraging SHE-enabled Domain Wall Motion Devices,Microelectronics Journal, Vol. 81, pp. 137–143, November 2018.
  33. F. Alghareb, R. A. Ashraf, and R. F. DeMara, “Designing and Evaluating Redundancy-based Soft Error Masking on a Continuum of Energy versus Robustness,IEEE Transactions on Sustainable Computing, Vol. 3, No. 3, pp. 139 – 152, July – September 2018.
  34. S. Salehi, M. Mashhadi, A. Zaeemzadeh, N. Rahnavard, and R. F. DeMara, “Energy-Aware Adaptive Rate and Resolution Sampling of Spectrally Sparse Signals Leveraging VCMA-MTJ Devices,IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 8, No. 4, July 2018, pp. 679 – 692.
  35. S. Angizi, H. Jiang, R. F. DeMara, J. Han, and D. Fan, “Majority-Based Spin-CMOS Primitives for Approximate Computing,IEEE Transactions on Nanotechnology (TNANO),Vol. 17, No. 4, July 2018, pp. 795 – 806.
  36. S. D. Pyle, K. Camsari, and R. F. DeMara, “Hybrid Spin-CMOS Stochastic Spiking Neuron for High-Speed Emulation of In-Vivo Neuron Dynamics,IET Computers & Digital Techniques (IEEE-indexed),Vol. 12, No. 4, July 2018, pp. 122 – 129, DOI: 10.1049/iet-cdt.2017.0145.
  37. A. Roohi, and R. F. DeMara, “NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths,IEEE Transactions on Computers,vol. 67, no. 7, pp. 949-959, 1 July 2018.
  38. S. Salehi, N. Khoshavi, and R. F. DeMara, “Mitigating Process Variability for Non-Volatile Cache Resilience and Yield,” IEEE Transactions on Emerging Topics,Vol. 8, No. 3, pp. 724 – 737, Jan. 2018.
    [pdf]
  39. R. F. DeMara, B. Chen, R. Hartshorne, and R. Thripp, “Elevating Participation and Outcomes with Computer-Based Assessments: An Immersive Development Workshop for Engineering Faculty,” ASEE Computers in Education Journal, Vol. 8, No. 3, pp. 1 – 12, July – September, 2017.
    [pdf]
  40. Y. Bai, R. F. DeMara, J. Di, and M. Lin, “Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm,” IEEE Transactions on Computers, on 8 November 2017.
    [pdf]
  41. R. Zand and R. F. DeMara, “Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance,” Journal of Physics D: Applied Physics, on 31 October 2017.
    [pdf]
  42. S. Pyle, D. Fan, and R. F. DeMara, “Compact Spintronic Muller C-Element with Near-Zero Standby Energy,” IEEE Transactions on Magnetics, on 23 October 2017.
    [pdf]
  43. R. Zand, A. Roohi and R. F. DeMara, “Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2394-2401, Sept. 2017.
    [pdf]
  44. B. Chen, R. F. DeMara, S. Salehi, and R. Hartshorne, “Elevating Learner Achievement Using Electronic Formative Assessments in the Engineering Laboratory: A Viable Alternative to Weekly Lab Reports,” IEEE Transactions on Education, Vol. PP, No. PP, in-press, Accepted 11 May 2017.
    [pdf]
  45. N. Khoshavi, R. A. Ashraf, R. F. DeMara, S. Kiamehr, F. Oboril, and M. B. Tahoori, “Contemporary CMOS Aging Mitigation Techniques: Survey, Taxonomy, and Methods,” Integration, the VLSI Journal, Volume 59, pp. 10 – 22, September 2017.
  46. A. Roohi, R. Zand, D. Fan and R. F. DeMara, “Voltage-based Concatenatable Full Adder using Spin Hall Effect Switching,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. PP, No. PP, in-press, Accepted 22 January 2017.
    [pdf]
  47. M. Krishna, R. Zand, A. Roohi, and R. F. DeMara, “Heterogeneous Energy-Sparing Reconfigurable Logic: Spin-based Storage and CNFET-based Multiplexing,” IET Circuits, Devices, and Systems,, Vol. 11, No. 3, pp. 274 – 279, June 2017.
    [pdf]
  48. R. F. DeMara, M. Platzner, and M. Ottavi, “Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures,” IEEE Transactions on Computers, Vol. PP, No. PP, in-press, June 2017.
    [pdf]
  49. R. F. DeMara, M. Platzner, and M. Ottavi, “Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures,” IEEE Transactions on Emerging Topics in Computing, Vol. PP, No. PP, in-press, June 2017.
    [pdf]
  50. A. M. Chabi, A. Roohi, H. Khademolhosseini, S. Sheikhfaal, S. Angizi, K. Navi, and R. F. DeMara, “Towards Ultra-efficient QCA Reversible Circuits, Microprocessors and Microsystems, Available online 15 November 2016: ISSN 0141-9331,
  51. A. J. Gonzalez, J. R. Hollister, R. F. DeMara, J. Leigh, B. Lanman, S. Y. Lee, S. Parker, C. Walls, J. Parker, J. Wong, C. Barham, and B. Wilder, “AI in Informal Science Education: Bringing Turing Back to Life to Perform the Turing Test,” International Journal of Artificial Intelligence in Education, Vol. 27, No. 3, pp. 353 – 384, March 2017.
  52. R. Zand, A. Roohi, D. Fan and R. DeMara, “Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables, IEEE Transactions on Nanotechnology, vol.PP, no.99, pp.1-1, Available online 07 November 2016: TNANO.2016.2625749,
    [pdf]
  53. X. Chen, N. Khoshavi, R. F. DeMara, J. Wang, D. Huang, W. Wen, and Y. Chen, “Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache, IEEE Transactions on Computers, vol.PP, no.99, pp.1-1, Available online 04 November 2016: TC.2016.2625245,
  54. S. Salehi, D. Fan, and R. F. DeMara, “Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency,” ACM Journal on Emerging Technologies in Computing Systems, in-press, accepted 13 September, 2016.
    [pdf]
  55. R. Oreifej, R. Al-Haddad, R. Zand, R. A. Ashraf, and R. F. DeMara, “Survivability Modeling and Resource Planning for Self-Repairing Reconfigurable Device Fabrics,” IEEE Transactions on Cybernetics, in-press, accepted 23 August, 2016.
  56. M. Alawad, Y. Bai, M. Lin, and R. F. DeMara, “Robust Large-Scale Convolution through Stochastic-Based Processing Without Multipliers, IEEE Transactions on Emerging Topics in Computing, in-press, accepted 12 August, 2016. Pre-print available at: 10.1109/TETC.2016.2601220, 2016
    Selected to IEEE Transactions Special Issue/Section on Approximate and Stochastic Computing Circuits, Systems and Algorithms.
  57. A. Roohi,R. Zand, S. Angizi, and R. F. DeMara, “A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency, IEEE Transactions on Emerging Topics in Computing, in-press, accepted 18 July, 2016. Selected to IEEE Transactions Special Issue/Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
    [pdf]
  58. S. D. Pyle, H. Li, and R. F. DeMara, “Compact Low-Power Instant Store and Restore D Flip-Flop using a Self-Complementing Spintronic Device,” IET Electronics Letters in-press, accepted 9 May, 2016. Pre-print available at: 10.1049/el.2015.4114, 2016
    [pdf]
  59. F. Alghareb, R. A. Ashraf, A. Alzahrani, R. F. DeMara, “Energy and Delay Tradeoffs of Soft Error Masking for 16nm FinFET Logic Paths: Survey and Impact of Process Variation in Near Threshold Region,” IEEE Transactions on Circuits and Systems II in-press, accepted 16 April, 2016
    [pdf]
  60. A. Roohi,R. Zand, and R. F. DeMara, “A Tunable Majority Gate based Full Adder using Current-Induced Domain Wall Nanomagnets, IEEE Transactions on Magnetics, Vol. 52, No. 8, 2016. Pre-print available at: 10.1109/TMAG.2016.2540600, 2016
    [pdf]
  61. V. Thangavel, Z. Song, and R. F. DeMara, “Intrinsic Evolution of Truncated Puiseux Series on a Mixed-Signal Field Programmable SoC,” IEEE Access, accepted 25 February 2016, in-press
    [pdf]
  62. R. Zand, A. Roohi, S. Salehi, and R. F. DeMara, “Scalable Adaptive Spintronic Reconfigurable Logic using Area-Matched MTJ Design,” IEEE Transactions on Circuits and Systems II, Vol. 63, No. 7, 2016, pp. 678 – 682. Pre-print available at: 10.1109/TCSII.2016.2532099, 2016
    [pdf]
  63. A. Alzahrani, and R. F. DeMara, “Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics using Design Disjunction,” IEEE Transactions on Computers 2016
    [pdf]
  64. A. Roohi, H. Thapliyal, and R. F. DeMara, “Wire crossing constrained QCA circuit design using bilayer logic decomposition,” Electronics Letters, Vol. 51, No. 21, October 2015, pp. 1677-1679.
    [pdf]
  65. H. Shabani, A. Roohi, A. Reza, M. Reshadi, N. Bagherzadeh, and R. F. DeMara, “Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks,” IEEE Transaction on Computers, Vol. 65, No. 6, June 2016, pp. 1789 – 1801. Pre-print available at: 10.1109/TC.2015.2458866, Selected for Paper of the Month, including free download with hosted companion video featured on IEEE Transactions webpage.
  66. M. Lin, S. Chen, R. F. DeMara, and J. Wawrzynek, “ASTRO: Synthesizing Application-Specific Reconfigurable Hardware Traces to Exploit Memory-Level Parallelism,” Microprocessors and Microsystems, in-press, corrected proof available online 26 March 2015.
  67. A. Roohi, R. F. DeMara, and N. Khoshavi, “Design and Evaluation of an Ultra-Area-Efficient Fault-Tolerant QCA Full Adder,” Microelectronics Journal, Vol. 46, No. 6, June 2015, pp. 531-542.
  68. M. Alawad, R. F. DeMara, and M. Lin, “Stochastically Estimating Modular Criticality in Large-Scale Logic Circuits Using Sparsity Regularization and Compressive Sensing,” Journal of Low Power Electronics and Applications, Vol. 5, No. 1, March 2015, pp. 3-37.
    [pdf][bibtex]
  69. Y. Bai, M. Alawad, R. F. DeMara, and M. Lin, “Optimally Fortifying Logic Reliability through Criticality Ranking,Electronics,vol. 4, no. 1, February 2015, pp. 150-172.
    [bibtex]
  70. N. Imran, R. A. Ashraf, and R. F. DeMara, “Power and Quality-Aware Image Processing Soft-Resilience using Online Multi-Objective GAs,” International Journal of Computational Vision and Robotics, Vol. 5, No. 1, January 2015, pp. 72 – 98.
    [pdf][bibtex]
  71. N. Imran, R. A. Ashraf, J. Lee, and R. F. DeMara, “Activity-based Resource Allocation for Motion Estimation Engines,” Journal of Circuits, Systems, and Computers, Vol. 24, No. 1, January 2015, pp. 1-32.
    [bibtex]
  72. N. Imran, and R. F. DeMara, “Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input,” International Journal of Reconfigurable Computing, vol. 2014, pp. 1-21, 2014.
    [pdf][bibtex]
  73. N. Imran, R. F. DeMara, J. Lee, and J. Huang, “Self-adapting Resource Escalation for Resilient Signal Processing Architectures,” The Springer Journal of Signal Processing Systems (JSPS), December 2014, Volume 77, Issue 3, pp. 257-280.
    [abstract] [pdf] [bibtex]
  74. A. J. Gonzalez, J. Leigh, R. F. DeMara, A. Johnson, S. Jones, S. Lee, V. Hung, L. Renambot, C. Leon-Barth, M. Brown, M. Elvir,
    J. Hollister and S. Kobosko, “Passing an Enhanced Turing Test Interacting with Lifelike Computer
    Representations of Specific Individuals
    ,” Journal of Intelligent Systems, vol. 22, no. 4, pp. 365-415, 2013.
    [pdf][bibtex]
  75. R. Ashraf, and R. F. DeMara, “Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms,” IEEE Transactions on Computers, vol.62, no.8, pp.1526-1541, Aug. 2013
    [abstract] [pdf] [bibtex]
  76. N. Imran, J. Lee and R. F. DeMara, “Fault Demotion Using Reconfigurable Slack (FaDReS),” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.21, no.7, pp.1364-1368, July 2013.
    [abstract] [pdf] [bibtex]
  77. N. Imran, J. Lee, Y. Kim, M. Lin, and R. F. DeMara, “Fault-Mitigation by Adaptive Dynamic Reconfiguration for Survivable Signal-Processing Architectures,” International Journal of Control and Automation (IJCA), Vol. 6, No. 2, Pages 111-120, April, 2013.
    [abstract] [pdf] [bibtex]
  78. C. A. Sharma, A. Sarvi, A. Al-Zahrani, and R. F. DeMara, “Self-Healing Reconfigurable Logic using Autonomous Group Testing,” Microprocessors and Microsystems, Volume 37, Issue 2, March 2013, pp. 174 – 184.
    [abstract] [bibtex]
  79. R.S. Oreifej and R.F. DeMara, “Intrinsic Evolvable Hardware Platform For Digital Circuit Design And Repair Using Genetic Algorithms,” Applied Soft Computing, 2012, Vol. 12, Issue 8, August 2012, pp. 2470 – 2480.
    [abstract] [bibtex]
  80. N. Imran, J. Lee, Y. Kim, M. Lin, and R. F. DeMara, “Amorphous Slack Methodology for Autonomous Fault-Handling in Reconfigurable Devices,” International Journal of Multimedia and Ubiquitous Engineering (IJMUE), Vol. 7, No. 4, Pages 29-44, October, 2012.
    [abstract] [pdf] [bibtex]
  81. R. Al-Haddad, R. Oreifej, R. A. Ashraf, and R. F. DeMara, “Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption,” International Journal of Reconfigurable Computing, vol. 2011, Article ID 430808, 25 pages, 2011.
    [abstract] [pdf] [bibtex]
  82. M.G. Parris, C.A. Sharma, and R. F. DeMara, “Progress in Autonomous Fault Recovery of Field Programmable Gate Arrays,” ACM Computing Surveys, Vol. 43 Issue 4, Article 31, October 2011.
    [abstract] [bibtex]
  83. R. F. DeMara, K. Zhang, and C. A. Sharma, “Autonomic Fault-Handling and Refurbishment Using Throughput-Driven Assessment,” Applied Soft Computing, Volume 11, Issue 2, Pages 1588-1599, March 2011.
    [abstract] [bibtex]
  84. W. Kuang, P. Zhao, J. S. Yuan, R. F. DeMara, “Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits,” IEEE Transactions on VLSI Systems, Vol. 18, No. 10, March, 2010, pp. 410 – 422
    [abstract] [pdf] [bibtex]
  85. J. Huang, M. Parris, J. Lee, and R. F. DeMara, “Scalable FPGA-based Architecture for DCT Computation Using Dynamic Partial Reconfiguration,” ACM Transactions on Embedded Computing Systems, Vol. 9, No. 1, Art. 9, October, 2009, pp. 1 – 18.
    [abstract] [bibtex]
  86. M. Georgiopoulos, R. F. DeMara, A. J. Gonzalez, A. S. Wu, M. Mollaghasemi, E. Gelenbe, M. Kysilka, J. Secretan, C. A. Sharma, and A. J. Alnsour, “A Sustainable Model for Integrating Current Topics in Machine Learning Research into the Undergraduate Curriculum,” IEEE Transactions on Education, Vol. 52, No. 4, November, 2009, pp. 503-512.
    [abstract] [pdf] [bibtex]
  87. Leon-Barth and R. F. DeMara, “Network Communication Effects Simulator Evaluation Scenarios for JTRS and WIN-T,” MSIAC Modeling and Simulation Journal, Vol. 2, No. 10, July, 2008, pp. 11 – 20.
    [abstract] [pdf] [bibtex]
  88. H. Tan, R. F. DeMara, “A Multi-layer Framework Supporting Autonomous Runtime Partial Reconfiguration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol. 16, No. 5, May, 2008, pp. 504 – 516.
    [abstract] [pdf] [bibtex]
  89. R. F. DeMara, Y. Tseng, and A. Ejnioui, “Tiered Algorithm for Distributed Process Termination Detection,” IEEE Transactions on Parallel and Distributed Systems, Vol. 18, No. 11, November, 2007, pp. 1529 – 1538.
    [abstract] [pdf] [bibtex]
  90. A. J. Rocke and R. F. DeMara, and S. Y. Foo, “Evaluation of Distributed File Integrity Analyzers in the Presence of Tampering,” International Journal of Network Security, Vol. 5, No. 1, pp.21-31, July, 2007.
    [abstract] [pdf] [bibtex]
  91. A. J. Gonzalez, M. Georgiopoulos, and R. F. DeMara, “Using Context-based Neural Networks to Maintain Coherence among Entities,” States in a Distributed Simulation,” The Journal of Defense Modeling and Simulation: Application, Methodology, Technology, Vol. 4, No. 2, April, 2007, pp. 1 – 26.
    [abstract] [pdf] [bibtex]
  92. T. Kocak, G. R. Harris, R. F. DeMara, “Self-timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion,” Journal of Circuits, Systems, and Computers, Vol. 16, No. 1, February 2007.
    [abstract] [pdf] [bibtex]
  93. A. J. Rocke and R. F. DeMara, “A Centralized Control and Dynamic Dispatch Architecture for File Integrity Analysis,” Journal of Systemics, Cybernetics and Informatics, Vol. 4, No. 6, January, 2007, pp. 1 – 7.
    [abstract] [pdf] [bibtex]
  94. J. Castro, J. Secretan, M. Georgiopoulos, R. F. DeMara, G. Anagnostopoulos, and A. J. Gonzalez, “Pipelining of Fuzzy-ARTMAP without Match-Tracking: Correctness, Performance Bound, and Beowulf Evaluation,” Neural Networks, Vol. 20, No. 1, January, 2007, pp. 109 – 128.
    [abstract] [pdf] [bibtex]
  95. R. F. DeMara, Y. Tseng, K. Drake, and A. Ejnioui, “Capability Classes of Barrier Synchronization Techniques,” International Journal of Computers and Applications, Vol. 28, No. 4, December, 2006, pp. 342 – 349.
    [abstract] [pdf] [bibtex]
  96. C. Leon-Barth, R. F. DeMara, and H. Marshall, “Communication Modeling of Training and Simulation Traffic in a Tactical Internet,” MSIAC Online Modeling and Simulation Journal, Vol. 1, No. 3, August, 2006, pp. 1 – 7.
    [abstract] [pdf] [bibtex]
  97. J. Di, J. S. Yuan, and R. F. DeMara, “Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application to FIR Design,” Integration, the VLSI Journal, Vol. 39, No. 2, March, 2006, pp. 90-112.
    [abstract] [pdf] [bibtex]
  98. A. J. Rocke and R. F. DeMara, “Mitigation of Insider Risks using Distributed Agent Detection, Filtering and Signaling,” International Journal of Network Security Vol. 5, No. 1, July, 2007, pp. 21 – 31.
    [abstract] [pdf] [bibtex]
  99. H. Fernlund, A. J. Gonzalez, R. F. DeMara, and M. Georgiopoulos, “Learning Tactical Human Behavior through Observation of a Human Actor,” IEEE Transactions on Systems, Man and Cybernetics, Vol. 36, No. 1, February, 2006, pp. 128 – 140.
    [abstract] [pdf] [bibtex]
  100. A. J. Rocke and R. F. DeMara, “A Collaborative Object Notification Framework for Insider Defense,” Journal of Autonomous Agents and Multi-Agent Systems, Vol. 12, No. 1, January, 2006, pp. 93 – 114.
    [abstract] [pdf] [bibtex]
  101. J. Castro, M. Georgiopoulos, J. Secretan, R. F. DeMara, G. Anagnostopoulos, and A. J. Gonzalez, “Parallelization of Fuzzy ARTMAP to Improve its Convergence Speed: The Network Partitioning Approach and the Data Partitioning Approach,” Nonlinear Analysis: Theory, Methods, and Applications, Vol. 63, No. 5 – 7, November – December, 2005, pp. 877-889.
    [abstract] [pdf] [bibtex]
  102. J. Castro, M. Georgiopoulos, and R. F. DeMara, “Data Partitioning using the Hilbert Space Filling Curves: Effect on the Speed of Convergence of Fuzzy ARTMAP for Large Database Problems,” Neural Networks Vol. 18, No. 7, September, 2005, pp. 967-984.
    [abstract] [pdf] [bibtex]
  103. H. A. Bahr and R. F. DeMara, “OTBSAF Scalability on Pentium III/4 and Athlon 64/XP3000 Architectures,” in MSIAC Modeling and Simulation Journal, on February 9, 2005, Vol.6, No. 3, March, 2005, pp. 1 – 4.
    [abstract] [pdf] [bibtex]
  104. J. Vargas, R. F. DeMara, A. J. Gonzalez, M. Georgiopoulos, and H. Marshall, “PDU Bundling and Replication for Reduction of Distributed Simulation Communication Traffic,” Journal of Defense Modeling and Simulation, Vol. 1, No. 3, August, 2004, pp. 171 – 183.
    [abstract] [pdf] [bibtex]
  105. A. J. Gonzalez, W. J. Gerber, R. F. DeMara, and M. Georgiopoulos, “Context-driven Near-term Intention Recognition,” Journal of Defense Modeling and Simulation, Vol. 1, No. 3, August, 2004, pp. 153 – 170.
    [abstract] [pdf] [bibtex]
  106. D. S. Carstens, P. McCauley-Bell, L. C. Malone, and R. F. DeMara, “Evaluation of the Human Impact of Password Authentication Practices on Information Security,” Informing Science Journal, Vol. 7, No. 1, August, 2004, pp. 67 -85.
    [abstract] [pdf] [bibtex]
  107. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, “Optimization of NULL Convention Self-timed Circuits,” Integration, The VLSI Journal, Vol. 37, No. 3, August, 2004, pp. 135 – 165.
    [abstract] [pdf] [bibtex]
  108. H. A. Bahr and R. F. DeMara, “Smart Priority Queue Algorithms for Self-optimizing Event Storage,” Simulation Modeling Practice and Theory, Vol. 12, No. 1, April, 2004, pp. 15 -40.
    [abstract] [pdf] [bibtex]
  109. R. F. DeMara and A. J. Rocke, “Mitigation of Network Tampering Using Dynamic Dispatch of Mobile Agents,” Computers and Security, Vol. 23, No. 1, February, 2004, pp. 31 – 42.
    [abstract] [pdf] [bibtex]
  110. Y. Tseng, R. F. DeMara, and P. Wilder, “Distributed-Sum Termination Detection Supporting Multithreaded Execution,” Parallel Computing, Vol. 29, No. 7, July, 2003, pp. 953 -968.
    [abstract] [pdf] [bibtex]
  111. W. Kuang, J. S. Yuan, R. F. DeMara, M. Hagedorn, and K. Fant, “Performance Analysis and Optimization of NCL Self-timed Rings,”IEE Proceedings on Circuits, Devices, and Systems, Vol. 150, No. 3, June, 2003, pp. 167 -172.
    [abstract] [pdf] [bibtex]
  112. R. C. Watkins, K. M. Reynolds, R. F. DeMara, M. Georgiopoulos, A. J. Gonzalez, and R. Eaglin, “Tracking dirty proceeds: exploring data mining technologies as tools to investigate money laundering,” Journal of Policing Practice and Research: An International Journal, Vol. 4, No. 2, January, 2003, pp. 163 – 178.
    [abstract] [pdf] [bibtex]
  113. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation,” Journal of Systems Architecture, Vol. 47, No. 12, June, 2002, pp. 977 – 998.
    [abstract] [pdf] [bibtex]
  114. R. F. DeMara and P. J. Wilder, “A Taxonomy of High Performance Computer Architectures for Uniform Treatment of Multiprocessor Designs,” Computers in Education Journal, Vol. XI, No. 4, October – December, 2001, pp. 45-52.
    [abstract] [pdf] [bibtex]
  115. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Delay-Insensitive Gate-level Pipelining,” Integration, The VLSI Journal, Vol. 30, No. 2, November, 2001, pp. 103 – 131.
    [abstract] [pdf] [bibtex]
  116. B. S. Motlagh and R. F. DeMara, “Performance of Scalable Shared-Memory Architectures,” Journal of Systems, Circuits, and Computers, Vol. 10, No. 1, February, 2000, pp. 1 -20.
    [abstract] [pdf] [bibtex]
  117. P. J. Wilder and R. F. DeMara, “Microprocessor-based parallel architectures using multiport-memory interconnection networks,” Journal of Engineering Technology, Vol. 16, No. 1, March, 1999, pp. 24 – 31.
    [abstract] [pdf] [bibtex]
  118. R. F. DeMara, R. Mercer, and M. Ebel, “Helical Latch for Scalable Boolean Logic Operations,” Nanotechnology, Vol. 5, No. 3, July, 1994, pp. 137 – 156.
    [abstract] [pdf] [bibtex]
  119. S. H. Chung, D. I. Moldovan, and R. F. DeMara, “A Parallel Computational Model for Integrated Speech and Natural Language Understanding,” IEEE Transactions on Computers, Vol. 42, No. 10, October, 1993, pp. 1171 – 1183
    [abstract] [pdf] [bibtex]
  120. R. F. DeMara and D. I. Moldovan, “The SNAP-1 Parallel AI Prototype,” IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 8, August, 1993, pp. 841-854.
    [abstract] [pdf] [bibtex]