Conferences

1. R. Yarnell, M. Hossain, R. F. DeMara, and Y. Bai, “Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator Framework”, in Proc. IEEE International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, April 5 – 7, 2023, doi: TBD.
2. M. Hossain, A. Tatulian, H. Thummala, R. F. DeMara, and S. Salehi, “Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy”, in Proc. IEEE International Symposium of Circuits and Systems (ISCAS), Monterey, CA, USA, May 21 – 25, 2023, doi: TBD.
3. L. O. Campbell, J. R. Rujimora, E. Laguardia, and R. F. DeMara, “Developing a Culturally Relevant Instructional Approach Self-efficacy Scale.” in Proceedings of Society for Information Technology & Teacher Education (SITE) International Conference of the Association for the Advancement of Computing in Education (AACE), pp. 2552-2556, New Orleans, LA, USA, March 13 – 17, 2023.
4. M. Nader, R. F. DeMara and H. Oonge, “Transfer Student Higher Success with Multiple- Attempt Testing in Engineering Dynamics,” in Proceedings of American Society for Engineering Education (ASEE-SE-2023), Fairfax, VA, USA, March 12 – 14, 2023.
6. M. Nader, R. F. DeMara, and A. Tatulian, “Quantitative Impacts and Student Perceptions of Offering MultiAttempt Lockdown Assessment in Two Engineering Core Courses: Dynamics and Thermodynamics,” in Proceedings of American Society for Engineering Education (ASEE-SE-2023), Fairfax, VA, USA, March 12 – 14, 2023.
7. P. Amoruso, R. F. DeMara, L. O. Campbell, F. Hernandez, and A. Mejia, “Personalizing Digitized Assessments and Remediation using an Automated Micro-Credentialing Framework,” Online Learning Consortium (OLC) 2022 Conference on Accelerating Online Learning Worldwide, Orlando, FL, Nov. 15, 2022.
8. R. Yarnell, D. Brignac, Y. Fu, and R. F. DeMara, “Utilization of Data Augmentation Techniques to Enhance Learning with Sparse Datasets,” in Proceedings of IEEE Artificial Intelligence for Industries Conference,(AI4I-2022), Laguna Hills, CA, USA, September 19 – 21, 2022.
9. X. Ma, K. Han, Y. Yang, R. F. DeMara and Y. Bai, “Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural Network,” 2022 IEEE 35th International System-on-Chip Conference (SOCC), September 05 – 08, 2022, Belfast, United Kingdom, pp. 1-6, doi: 10.1109/SOCC56010.2022.9908125
10. D. Crumley, M. Hossain, K. Martin, F. Ivey, R. Yarnell, R. F. DeMara, and Y. Bai, “Rehosting YOLOv2 Framework for Reconfigurable Fabric-based Accelaration,” in Proceedings of IEEE SoutheastCon 2022 (SECon-2022), Mobile, AL,  March 26 – 28, 2022.
11. M. Nader and R. F. DeMara, “The Impact on Learning Outcomes using Three-Attempt Tests in an Engineering Undergraduate Core Course: Dynamics,” in Proceedings of American Society for Engineering Education (ASEE-SE-2022), Charleston, SC, USA, March 13 – 15, 2022.
12. M. Liu, M/ Yin, K. Han, S. Luo, M. Liu, R. F. DeMara, B. Yuan, and Y. Bai. “Algorithm and Hardware Co-Design Co-Optimization Framework for LSTM Accelerator using Fully Decomposed Tensor Train,” Work-in-Progress paper at 58^th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, December 5-9, 2021.
13. M. Hossain, S. Salehi, D. Mulvaney, and R. F. DeMara, “Embedded STT-MRAM Energy Analysis for Intermittent Applications using Mean Standby Duration,” in Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS-2021), Dubai, UAE, Nov. 28, 2021 – Dec. 1, 2021
14. S. Sheikhfaal, M. R. Vangala, A. Adepegba and R. F. DeMara, “Long Short-Term Memory with Spin-Based Binary and Non-Binary Neurons,” in Proceedings of 64^th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 317-320, Virtual Modality due to pandemic restrictions, August 9-12, 2021, doi: 10.1109/MWSCAS47672.2021.9531773.
15. M. Liu, S. Luo, K. Han, B. Yuan, R. F. DeMara, and Y. Bai, “An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design.” In Proceedings of 32^nd IEEE International Conference on Application-specific Systems, Architectures and Processors (IEEE ASAP). Virtual Modality due to pandemic restrictions, July 7-8, 2021. Invited paper.
16. A. Tatulian and R. F. DeMara, “A Reconfigurable and Compact Spin-Based Analog Block for Generalizable n^th Power and Root Computation,” 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2021, pp. 302-307, doi: 10.1109/ISVLSI51109.2021.00062.
17. M. Liu, K. Han, S. Luo, M. Pan, M. Hossain, B. Yuan, R. F. DeMara, and Y. Bai, “An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset,” in Proceedings of Great Lakes Symposium on VLSI, pp. 391-396. Virtual Modality due to pandemic restrictions, June 22-25, 2021.
18. L. O. Campbell, R. Hartshorne, and R. F. DeMara, ”Digitally Mediated Team Learning: Foundational Perspectives – Book Shares on Designing Learning for Everyone,” Book Share Session Presentation at Association for Educational Communications and Technology, Chicago, IL, USA, November 2-6, 2021. (international)
19. G. Camero, S. Salehi, and R. DeMara, “Behavioral Simulation Educational Framework for 2-Terminal MTJ-based Analog to Digital Converter,” in Proceedings of IEEE Integrated STEM Education Conference (ISEC-2020) Princeton, NJ, USA, March 28, 2020 (original conference date prior to COVID-19 restrictions).
20. P. Wood, H. Pourmeidani, and R. F. DeMara, “Modular Simulation Framework for Process Variation Analysis of MRAM-based Deep Belief Networks,” in Proceedings of IEEE SoutheastCon 2019 (SECon-2019) ORaleigh, NC, March 11 – 15, 2020 (original conference date prior to COVID-19 restrictions).
21. R. F. DeMara, S. Silvermann, M. Reddy-Vangala, and M. Hossain, “Imparting Future Workforce Skills using Virtualized Active Learning: A Case Study in an Engineering Core Course,” Florida Online Innovation Summit (FOIS-2020) Orlando, FL, USA, March 3, 2020.
22. A. Tatulian, S. Salehi, and R. F. DeMara, “Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing,” in Proceedings of
    IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig-2019) Cancun, Mexico, December 9 – 11, 2019.
    [pdf]
23. G. Camero, S. Salehi, and R. DeMara, “A Spin-based Analog to Digital Converter Interactive Simulation Framework,” in Proceedings of
    IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig-2019 poster with abstract) Cancun, Mexico, December 9 – 11, 2019.
24. R. F. DeMara and S. Salehi, “Workshop on Virtualized Active Learning in STEM,” in Proceedings of
    IEEE Conference on Frontiers in Education (FIE-2019) Cincinnati, OH, USA, October 16 – 19, 2019.
    [pdf]
25. S. Salehi and R. F. DeMara, “Virtualized Active Learning for Undergraduate Engineering Disciplines (VALUED): A Pilot in a Large Enrollment Classroom,” in Proceedings of
    IEEE Conference on Frontiers in Education (FIE-19) Cincinnati, OH, USA, October 16 – 19, 2019.
    [pdf]
26. R. F. DeMara, L. O. Campbell, R. Hartshorne, and S. Spiegel, “Workshop on Digitally-Mediated Team Learning: Advancing Collaborative Problem-Solving within the STEM Classroom,” in Proceedings of
    NSF Conference on Cyberlearning (CL-2019) Alexandria, VA, USA, October 3 – 4, 2019.
27. V. R. Ostwal, R. Zand, R. F. DeMara, and J. Appenzeller, “”Binary Stochastic Neuron and Compound Synapse using Spin-orbit Torque Devices,” at
    TECHCON 2019 Austin, TX, USA, September 8 – 10, 2019.
28. S. Sheikhfaal, S. D. Pyle, S. Salehi, and R. F. DeMara, “An Ultra-Low Power Spintronic Stochastic Spiking Neuron with Self-Adaptive Discrete Sampling,” in Proceedings of
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS-2019) Dallas, TX, USA, Aug. 4 – 7, 2019.
29. R. F. DeMara, L. O. Campbell, R. Hartshorne, S. Spiegel, and J. G. Katz, “Community Report on Digitally-Mediated Team Learning,”
    National Science Foundation (NSF) Center for Innovative Research in Cyberlearning (CIRCL) Rapid Community Report August 1, 2019.
30. A. Roohi and R. F. DeMara, “IRC: Cross-layer design exploration of Intermittent Robust Computation for IoT Datapaths,” in Proceedings of
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2019) Miami, FL, U.S.A., July 15 – 17, 2019.
31. S. Salehi, A. Zaeemzadeh, A. Tatulian, N. Rahnavard, and R. F. DeMara, “MRAM-based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications,” in Proceedings of
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2019) Miami, FL, U.S.A., July 15 – 17, 2019.
32. S. Salehi, R. Zand, and R. F. DeMara, “Learner Capstone Panels for Immersing Undergraduates in Mechanisms of Engineering Research,” in Proceedings of
    American Association for Engineering Education Annual Conference (ASEE-2019), Tampa, FL, USA, June 16 – 19, 2019.
    [pdf]
33. R. F. DeMara, T. Tian, S. Sheikhfaal, and W. Howard, “Adapting Mixed-Mode Instructional Delivery to Thrive within STEM Curricula,” in Proceedings of
    American Association for Engineering Education Annual Conference (ASEE-2019), Tampa, FL, USA, June 16 – 19, 2019.
    [pdf]
34. S. Sheikhfaal, S. D. Pyle, and R. F. DeMara, “A High-Speed Ultra-Low-Power Subthreshold Spintronic Stochastic Spiking Neuron,” in Proceedings of
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS-2019) Dallas, TX, USA, Aug. 4 – 7, 2019.
35. R. F. DeMara, J. E. Beck, L. O. Campbell, R. Hartshorne, S. Spiegel, Z. Chen, M. Dagley, E. Hernandez, T. Tian, T. Gibson, S. Sheikhfaal, A. Tatulian, H. Pourmeidani, and H. Esteves,
    “Methods and Outcomes of the NSF Project on Synthesizing Environments for Digitally-Mediated Team Learning,” in Proceedings of
    American Association for Engineering Education Annual Conference (ASEE-2019), Tampa, FL, USA, June 16 – 19, 2019.
    [pdf]
36. S. Sheikhfaal and R. F. DeMara, “Leveraging Emerging Device Characteristics in Neuromorphic Computation: Stochasticity, Non-Volatility, and Area,”
    ACM Design Automation Conference (DAC-2019) Richard Newton poster presentation, Las Vegas, NV, June 2 – 6, 2019.
37. F. Alghareb and R. F. DeMara, “Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage,” in Proceedings of
    28th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI-2019), Washington DC, USA, May 8 – 10, 2019.
38. S. Salehi, R. Zand, and R. F. DeMara, “Clockless Spin-based Look-Up Tables with Wide Read Margin,” in Proceedings of
    28th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI-2019), Washington DC, USA, May 8 – 10, 2019.
39. S. Salehi, R. Zand, A. Zaeemzadeh, N. Rahnavard, and R. F. DeMara, “AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Spectrally Sparse Signals,” in Proceedings of
    28th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI-2019), Washington DC, USA, May 8 – 10, 2019.
40. A. Adepegba, R. Zand, and R. F. DeMara, “Noise Sensitivity Analysis of Deep Belief Networks: A Monte Carlo Simulation for Memristive Crossbars,” in Proceedings of
    2019 IEEE Southeastern Conference (SECon-2019) Huntsville, AL, USA, April 11 – 14, 2019.
41. M. Eisinger, R. Zand, and R. F. DeMara, “Training Optimization of Restricted Boltzmann Machines using a Contrastive Divergence Algorithm,” in Proceedings of
    2019 IEEE Southeastern Conference (SECon-2019) Huntsville, AL, USA, April 11 – 14, 2019.
42. R. F. DeMara, T. Tian S. Salehi, N. Khoshavi, and S. D. Pyle, “Scalable Delivery and Remediation of Engineering Assessments using Computer-Based Testing,” in Proceedings of
    IEEE Integrated STEM Education Conference (ISEC) Princeton, NJ, USA, March 16, 2019.
    [pdf]
43. M. Nader, R. F. DeMara, A. Tatulian, and B. Chen, “Quantitative Impact on Learning Achievement of High Integrity Testing during Online Delivery,” in Proceedings of
    American Society for Engineering Education Southeastern Conference (ASEE-SE-19) Raleigh, NC, USA, March 10 – 12, 2019.
    [pdf]
44. A. Roohi, S. Angizi, D. Fan, and R. F. DeMara, “SOT-MRAM Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, Throughput, and Power-Intermittency Resilience,” in Proceedings of the
    20th IEEE International Symposium on Quality Electronic Design (ISQED) Santa Clara, CA, March 6 – 7, 2019.
45. R. Zand and R. F. DeMara, “HSC-FPGA: A Hybrid Spin/Charge FPGA Leveraging the Cooperating Strengths of CMOS and MTJ Devices,” in Proceedings of the
    27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 24 – 26, 2019.
46. R. F. DeMara, B. Chen, and R. Hartshorne, “Elevating Participation and Outcomes with Digitized Assessments In Large-Enrollment Foundational STEM Curricula: An Immersive Development Workshop For Stem Faculty,”
    Online Learning Consortium Accelerating Learning Conference (OLC-2018), Orlando, FL, USA, November 14 – 17, 2018.
47. R. Zand and R. F. DeMara, “SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks,“ in Proceedings of the
    IEEE International Conference on Rebooting Computing (ICRC-2018), Washington, DC, USA, November 7 – 9, 2018, pp. 1 – 8.
48. S. Salehi and R. F. DeMara, “BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications,“ in Proceedings of the
    IEEE International Conference on Computer Design (ICCD-2018), Orlando, FL, USA, October 7 – 10, 2018.
49. T. Tian, R. F. DeMara, and S. Gao, “Lockdown Computerized Testing Interwoven with Rapid Remediation: A Crossover Study within a Mechanical Engineering Core Course,“ in Proceedings of the
    IEEE Conference on Frontiers in Education (FIE-18), San Jose, CA, USA, October 3 – 6, 2018.
50. R. F. DeMara, D. Turgut, E. Nassiff, S. Bacanli, and Neda H. Bidoki, “Automated Formation of Peer Learning Cohorts using Computer-Based Assessment Data: A Double-Blind Study within a Software Engineering Course,” in Proceedings of American Association for Engineering Education Annual Conference (ASEE-18), Salt Lake City, UT, USA, June 24 – 27, 2018.
    
51. T. Tian and R. F. DeMara, “High-Fidelity Digitized Assessment of Heat Transfer Fundamentals using a Tiered Delivery Strategy,” in Proceedings of American Association for Engineering Education Annual Conference (ASEE-18), Salt Lake City, UT, USA, June 24 – 27, 2018.
    
52. A. Roohi and R. F. DeMara, “Intermittent Computation for Energy-Harvesting-Powered Devices Using Selectively Non-Volatile Datapaths,”
    ACM//IEEE 55th Design Automation Conference (DAC) (Poster presentation only), San Francisco, CA USA, June 24 – 28, 2018.
53. R. Zand, K. Y. Camsari, S. D. Pyle, I. Ahmed, C. H. Kim, and R. F. DeMara “Low-Energy Deep Belief Networks using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons,” in Proceedings of 28th ACM Great Lakes Symposium on VLSI (GLSVLSI 2018), Chicago, Illinois, USA, May 23-25, 2018.
    [pdf]
54. A. Roohi, R. Zand, and R. F. DeMara “Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design,” in Proceedings of 28th ACM Great Lakes Symposium on VLSI (GLSVLSI 2018), Chicago, Illinois, USA, May 23-25, 2018.
    [pdf]
55. S. Angizi, Z. He, Y. Bai, J. Han, M. Lin, R. F. DeMara, and D. Fan, “Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neuromorphic Computing,“ in Proceedings of the
    28th ACM Great Lakes Symposium on VLSI (GLSVLSI 2018), Chicago, Illinois, USA, May 23-25, 2018.
56. F. Alghareb, R. Zand, and R. F. DeMara, “Synthesis of Normally-Off Boolean Circuits: An Evolutionary Optimization Approach Utilizing Spintronic Devices,“ in Proceedings of the
    IEEE SoutheastCon 2018 (SECon-2018), St. Petersburg, FL, USA, April 19 – 22, 2018.
57. S. D. Pyle and R. F. DeMara, “An Analysis of Voltage-Driven Spintronic Device Concatenation Through Spin Pumping,” poster with abstract atIEEE SoutheastCon 2018 (SECon-2018), St. Petersburg, FL, USA, April 19 – 22, 2018.
58. R. F. DeMara and R. A. Ashraf, “Self-Organizing Middleware for Extreme Heterogeneity: The Role of Technology-Oblivious Machine Learning Approaches to Realize Autonomous Resource Adaptation,”
    position paper to DOE Extreme Heterogeneity Workshop (WEH-18), Gaithersburg, MD, January 23 – 25, 2018.
59. R. F. DeMara, “Heterogeneous Technology Configurable Fabrics: A Field-Programmable Paradigm for Leveraging Post-CMOS Devices in HPC,” position paper to
    DOE Extreme Heterogeneity Workshop (WEH-18), Gaithersburg, MD, January 23 – 25, 2018.
60. A. Roohi, R. Zand, and R. F. DeMara, “Synthesis of Normally-Off Boolean Circuits: An Evolutionary Optimization Approach Utilizing Spintronic Devices,“ in Proceedings of the
    19th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 13 – 14, 2018.
61. B. Chen, R. F. DeMara, and R. Hartshorne, “Developing Computer-based Assessments for Large-Enrollment Classes: A Faculty Workshop for STEM Disciplines,” in Proceedings of American Educational Research Association Annual Meeting (AERA-2018), April 13 – 17, 2018, New York, NY, USA.
    
62. T. Tian and R. F. DeMara, “Matrix-Organized Instructional Delivery for Scaling-up Problem-based Learning through Reallocation of Instructional Support,” in Proceedings of American Society for Engineering Education Southeastern Conference (ASEE-SE-18), Daytona Beach, FL, March 4 – 6, 2018.
    [pdf]
63. R. F. DeMara, A. Roohi, R. Zand, S. D. Pyle, “Heterogeneous Technology Configurable Fabrics for Field Programmable Co-design of CMOS and Spin-based Devices,” in Proceedings of IEEE International Conference on Rebooting Computing (ICRC-2017), Washington, DC, USA, November 8 – 9, 2017.
    [pdf]
64. A. Roohi, L. Wang, S. Kose, and R. F. DeMara “Secure Intermittent-Robust Computation for Energy Harvesting Device Security and Outage Resilience,” in Proceedings of 14th IEEE International Conference on Advanced and Trusted Computing (ATC 2017) San Francisco, CA, USA, August 4, 2017.
    [pdf]
65. R. A. Ashraf, R. Gioiosa, G. Kestor, R. F. DeMara, “Exploring the Effect of Compiler Optimizations on the Reliability of HPC Applications,“ in Proceedings of 22nd IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems (IEEE DPDNS 2017) Orlando, FL, USA, June 2, 2017.
    
66. R. Thripp, R. F. DeMara, R. Hartshorne, B. Chen, “Fortifying Asynchronous Online Learning with Digitally Delivered In-Person Assessments to Leverage the Testing Effect within Undergraduate Engineering Courses,” (presentation only), International Conference on e-Learning (ICEL) Orlando, FL, USA, June 1 – 2, 2017.
    [pdf]
67. S. Salehi and R. F.DeMara, “Process Variation Immune and Energy Aware Sense Amplifiers for Resistive Non-Volatile Memories,” in Proceedings of IEEE International Symposium on Circuits & Systems (ISCAS-2017) Baltimore, MD, USA, May 28–31, 2017.
    [pdf]
68. Y. Bai, S. Hu, R. F. DeMara, and M. Lin, “A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture,“ in Proceedings of 27th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI-2017) Banff, Alberta, Canada, May 10–12, 2017.
    
69. F. Alghareb, R. A. Ashraf, A. Al-Zahrani, and R. F. DeMara, “Energy and Delay Tradeoffs of Soft Error Masking for 16nm FinFET Logic Paths: Survey and Impact of Process Variation in Near Threshold Region,“ IEEE International Symposium on Circuits & Systems (ISCAS-2017) lecture presentation, Baltimore, MD, USA, May 28–31, 2017.
    
70. R. F. DeMara, “Heterogeneous Technology Configurable Fabrics: Leveraging Reconfiguration as a Pathway Towards Emerging Devices,” IEEE Reconfigurable Architectures Workshop (RAW-2017), Keynote Speech (invited presentation with IEEExplore-indexed abstract), 29 May 2017, Orlando, FL, USA.
    [pdf]
71. N. Khoshavi, S. Salehi, and R. F. DeMara, “Variation-Immune Resistive Non-Volatile Memory using Self-Organized Sub-Bank Circuit Designs,” in Proceedings of 18th International Symposium on Quality Electronic Design (ISQED-2017), Santa Clara, CA, USA, March 13 – 15, 2017.
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72. S. Angizi, Z. He, R. F. DeMara, D.Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,“ in Proceedings of 18th International Symposium on Quality Electronic Design (ISQED-2017), Santa Clara, CA, USA, March 13 – 15, 2017.
    
73. R. Hartshorne, R. F. DeMara, and B. Chen, “Strategies and Lessons Learned from a Faculty Development Pilot Program for Computerizing Assessments in Engineering Curricula,” in Proceedings of 27th Annual Conference of the Society for Information Technology and Teacher Education (SITE-2016), Austin, TX, USA, March 5 – 9, 2017.
    
74. R. F. DeMara, R. Hartshorne, B. Chen, R. Zand, “Digitizing and Remediating Engineering Assessments: An Immersive and Transportable Faculty Development Experience,” in Proceedings of American Association for Engineering Education National Conference (ASEE-17), Columbus, OH, USA, June 25-28, 2017.
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75. R. F. DeMara, S. Salehi, R. Hartshorne, B. Chen, “GLASS: Group Learning At Significant Scale via WiFi-Enabled Learner Design Teams in an ECE Flipped Classroom,” in Proceedings of American Association for Engineering Education National Conference (ASEE-17), Columbus, OH, USA, June 25-28, 2017.
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76. S. Kose, L.Wang, and R. F. DeMara, “On-Chip Sensor Circle Distribution Technique for Real-Time Hardware Trojan Detection,” poster-only presentation at Government Microcircuit Applications & Critical Technology Conference (GOMACTech – 2017), Reno, NV, USA, March 20-23, 2017.
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77. R. Gioiosa, R. A. Ashraf, G. Kestor, R. F. DeMara, C.-Y. Cher, and P. Bose, “Modeling Fault Propagation in HPC Applications,” Workshop on Modeling & Simulation of Systems and Applications (ModSim-2016), (presentation with abstract), Seattle, August 10 – 12, 2016.
    
78. R. F. DeMara and M. Lin, “Heterogeneous Technology Fabric,” 2016 Command, Control, Communications, Computers, Intelligence (C4I) and Cyber Conference, (poster only presentation), Utica, New York, U.S.A., June 14 – 16, 2016. National.
    
79. F. S. Alghareb, M. Lin, and R. F. DeMara, “Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs,” in Proceedings of the International Symposium on VLSI (ISVLSI-2016), Pittsburgh, Pennsylvania, U.S.A., July 11-13, 2016.
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80. R. F. DeMara, N. Khoshavi, S. Pyle, J. Edison, R. Hartshorne, B. Chen, M. Georgiopoulos, “Redesigning Computer Engineering Gateway Courses using a novel Remediation Hierarchy,” in Proceedings of American Association for Engineering Education National Conference (ASEE-16), New Orleans, LA, USA, June 26 – 29, 2016.
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81. X. Chen, N. Khoshavi, J. Zhou, D. Huang, R. F. DeMara, J. Wang, W. Wen, and Y. Chen“AOS: Adaptive Overwrite Scheme for Energy-Efficient MLC STT-RAM Cache,” in Proceedings of 53rd Design Automation Conference (DAC 2016), Austin, Texas, June 5-9, 2016.
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82. R. A. Ashraf, N. Khoshavi, A. Alzahrani, R. F. DeMara, S. Kiamehr and M. B. Tahoori, “Area-Energy Tradeoffs of Logic Wear-Leveling for BTI-induced Aging,” in Proceedings of ACM Computing Frontiers, Como, Italy, May 16 – 18, 2016.
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83. R. Hartshorne, B. Chen, J. Edison, and R. F. DeMara, “Flipping the computer engineering gateway courses: A discussion of the processes and results,” in Society for Information Technology & Teacher Education International Conference (SITE 16), Savannah, GA, United States, Mar 21, 2016.
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84. X. Chen, N. Khoshavi, R. F. DeMara, J. Wang, W. Wen, and Y. Chen, “A Selective Overwrite Scheme to Mitigate Write Disturbance for Energy Efficient MLC STT-RAM,” 2016 Non-Volatile Memories Workshop (NVMW-2016), March 6 – 8, 2016. Presentation only; no proceedings.
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85. N. Khoshavi, X. Chen, J. Wang, and R. F. DeMara, “Bit-Upset Vulnerability Factor for eDRAM Last Level Cache Immunity Analysis,” in Proceedings of 17th International Symposium on Quality Electronic Design (ISQED 2016), Santa Clara, CA, USA, March 15 – 16, 2016.
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86. R. F. DeMara, S. Salehi, N. Khoshavi, R. Hartshorne, and B. Chen, “Strengthening STEM laboratory assessment using student-narrative portfolios interwoven with online evaluation,” in the American Society for Engineering Education Southeast Section Conference (ASEE-SE 16), Tuscaloosa, AL, USA, March 13-15, 2016.
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87. R. F. DeMara, S. Salehi, and S. Muttineni, “Exam Preparation through Directed Video Blogging using Electronically-Mediated Realtime Classroom Interaction,” in The American Society for Engineering Education Southeast Section Conference (ASEE-SE 16), Tuscaloosa, AL, USA, March 13-15, 2016.
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88. C. Labrado, H. Thapliyal, and R. F. DeMara, “Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing,” in Proceedings of International Symposium on Nanoelectronic and Information Systems (INIS-2015), pp. 117 – 111, Indore, India, December 21 – 23, 2015.
    
89. R. A. Ashraf, R. Gioiosa, G. Kestor, R. F. DeMara, C.-Y. Cher, and P. Bose, “Understanding the Propagation of Transient Errors in HPC Applications,” in Proceedings of 27th International Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing-2015), Austin, TX, Nov. 15 – 20, 2015.
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90. R. F. DeMara and C. A. Sharma, and R. A. Ashraf, “Secure Reconfigurable Logic Fabrics through Online Resource Sensing and Competition,” Florida Cybersecurity Symposium, (presentation with abstract), Tampa, FL, USA, October 13 – 14, 2015.
    
91. A. M. Chabi, A. Roohi, H. Khademolhosseini, S. Angizi, R. F. DeMara, and K. Navi, “Cost-Efficient QCA Reversible Combinational Circuits Based on a New Reversible Gate,” in IEEE Proceedings of International Symposium on Computer Architecture and Digital Systems (CADS-2015), pp. 1 – 6,Tehran, Iran, October 7 – 8, 2015.
    
92. A. Al-Zahrani and R. F. DeMara, “Hypergraph-Cover Diversity for Maximally-Resilient Reconfigurable Systems,” in Proceedings of 12th IEEE International Conference on Embedded Software and Systems (ICESS 2015), New York, USA, August 24 – 26, 2015.
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93. A. Al-Zahrani and R. F. DeMara, “Process Variation Immunity of Alternative 16nm HK/MG-based FPGA Logic Blocks,” in Proceedings of IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS-2015), Fort Collins, CO, USA, August 2 – 5, 2015.
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94. S. D. Pyle, V. Thangavel, S. M. Williams, and R. F. DeMara, “Self-Scaling Evolution of Analog Computation Circuits with Digital Accuracy Refinement,” in Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montreal, QC, Canada, June 15 – 18, 2015.
    [pdf]
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95. R. Al-Haddad, R. S. Oreifej, R. Zand, A. Ejnioui, and R. F. DeMara, “Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics,” in Proceedings of North American Test Workshop (NATW 2015), Johnson City, NY, May 11 – 13, 2015.
    [pdf]
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96. A. Roohi, R. F. DeMara, and N. Khoshavi, “Dual Computational Layer Based Logic Design for QCA Circuits,” in Proceedings of ACM/EDAC/IEEE 51st Design Automation Conference (DAC) Work-In-Progress session (poster presentation only), San Francisco, CA, USA, June 7 – 11, 2015.
    
97. A. A. Naseer, R. A. Ashraf, D. Dechev, and R. F. DeMara, “Designing Energy-Efficient Approximate Adders using Parallel Genetic Algorithms,”in Proceedings of IEEE SoutheastCon 2015 (SECon-2015), Fort Lauderdale, FL, April 9 – 12, 2015.
    [pdf]
    
98. S. Salehi, and R. F. DeMara, “Energy and Area Analysis of a Floating-Point Unit in 15nm CMOS Process Technology,” in Proceedings of IEEE SoutheastCon 2015 (SECon-2015), Fort Lauderdale, FL, April 9 – 12, 2015.
    [pdf]
    
99. R. A. Ashraf, A. Al-Zahrani, N. Khoshavi, R. Zand, S. Salehi, A. Roohi, M. Lin, and R. F. DeMara, “Reactive Rejuvenation of CMOS Logic Paths using Self-Activating Voltage Domains,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2015), Lisbon, Portugal, May 24 – 27, 2015.
    [pdf]
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100. K. Zhang, N. Khoshavi, J. M. Alghazo, and Ronald F. DeMara, “Organic Embedded Architecture for Sustainable FPGA Soft-Core Processors,” in Proceedings of IEEE 61st Reliability and Maintainability Symposium (RAMS-2015), Palm Harbor, FL, January 26 – 29, 2015.
     [pdf]
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101. R. Oreifej, R. Al-Haddad, R. A. Ashraf, and R. F. DeMara, “Sustainability Assurance Modeling for SRAM-based FPGA Evolutionary Self-Repair,” in Proceedings of IEEE International Conference on Evolvable Systems (ICES-2014),, pp. 17 – 22, Orlando, FL, December 9 – 12, 2014.[pdf][ppt]
     [bibtex]
102. N. Khoshavi, R. Ashraf, and R. F. DeMara, “Applicability of Power-gating Strategies for Aging Mitigation of CMOS Logic Paths,” in Proceedings of IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS-2014), pp. 929-932, College Station, TX, USA, 3-6 Aug. 2014.[pdf][pub]
     [bibtex]
103. R. A. Ashraf, A. Alzahrani, and R. F. DeMara, “Extending Modular Redundancy to NTV: Costs and Limits of Resiliency at Reduced Supply Voltage,” in Proceedings of Workshop on Near Threshold Computing (WNTC-2014), Minneapolis, MN, USA, June 14, 2014.
     [bibtex]
104. R. A. Ashraf, A. Alzahrani, and R. F. DeMara, “Exploring Spatial Redundancy to Mitigate Aging-Induced Timing Degradation,” ACM/EDAC/IEEE 51st Design Automation Conference (DAC), (poster presentation only), San Francisco, California, USA, June 1 – 5, 2014.
     [bibtex]
105. N. Imran, R. Ashraf, and R. F. DeMara, “Evaluating Quality and Resilience of an Embedded Video Encoder against a Continuum of Energy Consumption,” invited submission to 2014 Workshop on Suite of Embedded Applications and Kernels (SEAK-2014), San Francisco, California, USA, June 1, 2014.
106. M. Alawad, Y. Bai, R. F. DeMara, and M. Lin, “Energy-Efficient Multiplier-Less Discrete Convolver through Probabilistic Domain Transformation ,” in Proceedings of 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA-14), pp. 185-188, Monterey, California, USA, February 27-28, 2014. DOI=10.1145/2554688.2554769.
     [bibtex]
107. A. Al-Zahrani and R. F. DeMara, “Non-Adaptive Sparse Recovery and Fault Evasion using Disjunct Design Configurations ,” poster paper with abstract in Proceedings of
     22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA-14), Monterey, California, USA, February 27-28, 2014.
     [pdf] [bibtex]
108. R. Ashraf and R. F. DeMara, “Scalability of Modular Redundancy for Near-Threshold Computing,” Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH 2014), Orlando, Florida, USA, February 16th, 2014.
     [bibtex]
109. J. R. Hollister, S. L. Parker, A. J. Gonzalez, and R. F. DeMara, “An Extended Turing Test: A Context-Based Approach Designed to Educate Youth in Computing,” in Proceedings of the 8th International and Interdisciplinary Conference Modeling and Using Context (CONTEXT-2013), Annecy, France, October 28 – 31, 2013.Reprinted in P. Brézillon, P. Blackburn, and R. Dapoigny, editors, Modeling and Using Context, Springer Berlin Heidelberg Lecture Notes in Computer Science, ISBN: 978-3-642-40971-4, pp. 213 – 221.
     [pdf] [bibtex]
110. N. Imran, R. Ashraf, and R. F. DeMara, “On-demand Fault Scrubbing Using Adaptive Modular Redundancy,” The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2013), Las Vegas, Nevada, USA, July 22-25, 2013.
     [pdf] [ppt] [bibtex]
111. R. Ashraf, F. Luna, D. Dechev, and R. F. DeMara, “Designing digital circuits for FPGAs using parallel genetic algorithms,” 2012 Spring Simulation Multi-conference (SpringSim 2012), Orlando, FL, USA, March 25 – 28, 2012, paper #15.
     [abstract] [pdf] [bibtex]
112. J. Hollister, S. Parker, A. Gonzalez, R. F. DeMara, “Who Says it Best? A Comparison of Four Different Dialog Management Systems,” in Proceedings of 21st Annual Conference on Behavior Representation in Modeling Simulation (BRIMS 2012), Amelia Island, FL, USA, March 12–15, 2012, pp. 141 – 146.
113. N. Imran, J. Lee, Y. Kim, M. Lin, and R. F. DeMara, “Area-Efficient Fault-Handling for Survivable Signal-Processing Architectures,” in Proceedings of First International Conference on Advanced Signal Processing, pp. 37, Seoul, Korea, March 30–31, 2012.
     [abstract] [pdf] [ppt] [bibtex]
114. Rizwan A. Ashraf, Ouns Mouri, Rami Jadaa, R. F. Demara, “Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs”, in proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011), pp.99-104, Nov. 30 2011-Dec. 2 2011.
     [abstract] [pdf] [ppt] [bibtex]
115. N. Imran, R. F. Demara, “A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution”, in proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011), pp.398-403, Nov. 30 2011-Dec. 2 2011.
     [abstract] [pdf] [ppt] [bibtex]
116. N. Imran, R. F. Demara, “Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation”, in proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011), pp.61-66, Nov. 30 2011-Dec. 2 2011.
     [abstract] [pdf] [ppt] [bibtex]
117. Rizwan A. Ashraf, R. Oreifej and R. F. DeMara, “Scalability of Sustainable Self-Repair to Mitigate Aging Induced Degradation in SRAM-based FPGA Devices”, in presentations at the Revolutionary Electronics in Space (ReSpace) / Military and Aerospace Programmable Logic Devices (MAPLD) 2011 Conference, Albuquerque, NM, August 22-25, 2011.
     [abstract] [ppt] [bibtex]
118. N. Imran, and R. F. DeMara, “Cyclic NMR-based Fault Tolerance with Bitstream Scrubbing via Reed-Solomon Codes”, in presentations at the Revolutionary Electronics in Space (ReSpace) / Military and Aerospace Programmable Logic Devices (MAPLD) 2011 Conference, Albuquerque, NM, August 22-25, 2011.
     [abstract] [ppt] [bibtex]
119. N. Imran, and R. F. DeMara, “A Fault-Handling Methodology by Promoting Hardware Configurations via PageRank”, in presentations at the Revolutionary Electronics in Space (ReSpace) / Military and Aerospace Programmable Logic Devices (MAPLD) 2011 Conference, Albuquerque, NM, August 22-25, 2011.
     [abstract] [ppt] [bibtex]
120. V. Hung, A. Gonzalez, R. F. DeMara, “Dialog Management For Rapid-Prototyping of Speech-Based Training Agents”, Interservice/Industry Training, Simulation & Education Conference, Orlando, Florida, USA, Nov 29-Dec 2, 2010.
     [abstract] [pdf] [ppt] [bibtex]
121. R. F. DeMara, J. Lee, R. Al-Haddad, R. Oreifej, R. Ashraf, B. Stensrud, M. Quist, “Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors”, The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2010), Las Vegas, Nevada, USA, July 12-15, 2010.
     [abstract] [pdf] [ppt] [bibtex]
122. V. Hung, M. Elvir, A. J. Gonzalez and R. F. DeMara, “Toward a Method For Evaluating Naturalness in Conversational Dialog Systems”, IEEE International Conference on Systems, Man, and Cybernetics, San Antonio, Texas, October, 2009.
     [abstract] [pdf] [ppt] [bibtex]
123. D. Workman, R. F. DeMara, K. Sundaram, D. Turgut, I. Batarseh, and S. Bethel, “Preparing for the Accreditation Visit,” presented at ABET Best Assessment Processes Symposium, Indianapolis, IN, U.S.A, April 3-4, 2009.
     [abstract] [pdf] [ppt] [bibtex]
124. V. Hung, A. Gonzalez, and R. F. DeMara, “Towards A Context-Based Dialog Management Layer for Expert Systems,” in Proceedings of the International Conference on Information, Process, and Knowledge Management, Cancun, Mexico, February 1 -7, 2009.
     [abstract] [pdf] [ppt] [bibtex]
125. R. F. DeMara, A. J. Gonzalez, S. Jones, A. Johnson, J. Leigh, V. Hung, C. Leon-Barth, R. A. Dookhoo, L. Renambot, S. Lee, and G. Carlson, “Towards Interactive Training with an Avatar-based Human-Computer Interface”, in Proceedings of the 2008 Interservice/Industry Training Systems and Education Conference (I/ITSEC’08), Orlando, FL, U.S.A., December 1-4, 2008.
     [abstract] [pdf] [ppt] [bibtex]
126. A. Sarvi, C. A. Sharma, R. F. DeMara, “BIST-Based Group Testing For Diagnosis of Embedded FPGA Cores,” in Proceedings of the International Conference on Embedded Systems and Applications (ESA’08), Las Vegas, Nevada, U.S.A., July 14-17, 2008.
     [abstract] [pdf] [bibtex]
127. J. Huang, M. Parris, J. Lee, and R. F. DeMara, “Scalable FPGA Architecture for DCT Computation using Dynamic Partial Reconfiguration,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’08), Las Vegas, U.S.A., July 14-17, 2008.
     [abstract] [pdf] [ppt] [bibtex]
128. K. Zhang, R. F. DeMara, and J. Alghazo, “FPGA Self-Repair using an Organic Embedded System Architecture,” in Proceedings of the International Workshop on Dependable Circuits Design (DECIDE’07), Buenos Aires, Argentina, December 6-7, 2007.
     [abstract] [pdf] [ppt] [bibtex]
129. R. S. Oreifej, R. N. Al-Haddad, H. Tan, R. F. DeMara, “Layered Approach To Intrinsic Evolvable Hardware Using Direct Bitstream Manipulation Of Virtex II Pro Device,” “Best paper of session and nominated best of conference” in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL’07), Amsterdam, Netherlands, 27-29 August 2007, 2007.
     [abstract] [pdf] [ppt][bibtex]
130. R. N. Al-Haddad, C. A. Sharma, R. F. DeMara, “Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms ERSA ’07,, Las Vegas, Nevada, U.S.A, June 25 – 28, 2007.
     [abstract] [4-page version pdf] [5-page version pdf] [ppt] [bibtex]
131. R. S. Oreifej, C. A. Sharma, R. F. DeMara, “Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware,” in Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig’06), San Luis Potosi, Mexico, September 20-22, 2006, pp 106-113.
     [abstract] [pdf] [ppt] [bibtex]
132. R. F. DeMara, “Dynamic Runtime Reconfiguration for Evolvable Hardware,,” Keynote Speech at the IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig’06), San Luis Potosi, Mexico, September 20-22, 2006.
133. H. Tan, R. F. DeMara, “A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead,” in Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig-06), San Luis Potosi, Mexico, September 20-22, 2006, pp. 86-90.
     [abstract] [pdf] [ppt] [bibtex]
134. K. Zhang, G. Bedette, R. F. DeMara, “Triple Modular Redundancy with Standby (TMRSB) Supporting Dynamic Resource Reconfiguration,” in Proceedings of IEEE AUTOTESTCON 2006, September 18-21, 2006.
     [abstract] [pdf] [ppt] [bibtex]
135. H. Tan, R. F. DeMara, A. J. Thakkar, A. Ejnioui and J. D. Sattler, “Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: a Case Study,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’06), Las Vegas, Nevada, U.S.A, 2006.
     [abstract] [2-page pdf] [7-page pdf] [bibtex]
136. M. Georgiopoulos, E. Gelenbe, R. F. DeMara, A. J. Gonzalez, M. Kysilka, M. Mollaghasemi, A. S. Wu, G. Anagnostopoulos, I. Russell, J. Secretan “Assessing and Evaluating CRCD Experiences at the University of Central Florida: An NSF Project,” in Proceedings of the 2006 American Society for Engineering Education Annual Conference and Exposition (ASEE’06), Chicago, Illinois, U.S.A., June 18 – 21, 2006.
137. J. D. Sattler, M. Leftwich, R. F. DeMara, H. Tan, and A. Ejnioui, “Partial Reconfiguration of FPGAs with Software and Hardware Anti-Tamper Considerations,” in The proceedings of the 2006 DoD Anti-Tamper Conference (AT’06), April 25-27, 2006, Dayton, OH, U.S.A.
     [abstract] [pdf] [bibtex]
138. C. A. Sharma, R. F. DeMara, “A Combinatorial Group Testing Method for FPGA Fault Location”, International Conference on Advances in Computer Science and Technology (ACST 2006), Puerto Vallarta, Mexico, January 23 – 35, 2006
     [abstract] [pdf] [ppt] [bibtex]
139. C. J. Milliord, C. A. Sharma, R. F. DeMara, “Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic Devices,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig’05), pp. 8.1.1 – 8.1.6, Puebla City, Mexico, September 28 – 30, 2005.
     [abstract][pdf] [ppt] [bibtex]
140. K. Zhang, R. F. DeMara, C. A. Sharma, “Consensus-based Evaluation for Fault Isolation and On-line Evolutionary Regeneration,” in Proceedings of the International Conference in Evolvable Systems (ICES’05), pp. 12 -24, Barcelona, Spain, September 12 – 14, 2005.
     [abstract] [pdf] [ppt] [bibtex]
141. R. F. DeMara and K. Zhang, “Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration,” in Proceedings of the NASA/DoD Conference on Evolvable Hardware(EHW-05), Washington D.C., U.S.A., June 29 – July 1, 2005.
     [abstract] [pdf] [ppt][bibtex]
142. H. Tan and R. F. DeMara, “A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA-05), Las Vegas, Nevada, U.S.A, June 27-30, 2005.
     [abstract] [pdf] [ppt] [bibtex]
143. R. F. DeMara and C. A. Sharma, “Self-Checking Fault Detection using Discrepancy Mirrors,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-05), pp. 311-317, Las Vegas, Nevada, U.S.A, June 27-30, 2005.
     [abstract] [pdf] [ppt] [bibtex]
144. A. Ejnioui and R. F. DeMara, “Area Reclamation Metrics for SRAM-based Reconfigurable Device,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA-05), Las Vegas, Nevada, U.S.A, June 27 -30, 2005.
     [abstract] [pdf] [ppt] [bibtex]
145. M. Georgiopoulos, E. Gelenbe, R. DeMara, A. Gonzalez, M. Kysilka, M. Mollaghasemi, A. Wu, I. Russell, G . Anagnostopoulos, J. Secretan, “Progress on the CRCD Experience at the University o f Central Florida: An NSF Project,” in Proceedings of the ASEE 2005 Annual Conference and Exposition (ASEE’05), Session on Undergraduate Research & New Directions, pp. 1332: 1 – 8, Portland , Oregon , U.S.A., June 12 – 15 , 2005.
146. G. Wang, R. F. DeMara and A. J. Rocke, “Mobility-Enhanced File Integrity Analyzer For Networked Environments,” in Proceedings of the 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI ’05), Orlando, FL, July 10-13, 2005.
     [abstract] [pdf][pdf presentation] [bibtex]
147. A. Ejnioui and R. F. DeMara, “FPGA Defragmentation for Sustainable Performance in Reconfigurable Computers,” in Proceedings of the International Symposium on VLSI (ISVLSI-05),Tampa, Florida, U.S.A., May 11-12, 2005.
     [abstract] [pdf] [bibtex]
148. J. Castro, J. Secretan, M. Georgiopoulos, R. F. DeMara, G. Anagnostopoulos, and A. Gonzalez, “Pipelining Fuzzy ARTMAP without Match-Tracking,” in Proceedings of the 2004 Artificial Neural Networks in Engineering (ANNIE-04) Conference, St. Louis, Missouri, U.S.A., November 7-10, 2004.
     [abstract] [pdf] [bibtex]
149. J. Castro, M. Georgiopoulos, R. F. DeMara and A. J. Gonzalez, “A Data Partitioning Approach to speed up the Fuzzy ARTMAP algorithm using the Hilbert Space-Filling Curve,” in Proceedings of the 2004 International Joint Conference on Neural Networks (IJCNN-04), Budapest, Hungary, July 25-29, 2004.
     [abstract] [pdf] [bibtex]
150. J. Castro, M. Georgiopoulos, J. Secretan, R. F. DeMara, G. Anagnostopoulos, and A. J. Gonzalez, “Parallelization of Fuzzy ARTMAP to Improve its Convergence Speed: The Boxing Approach and the Data Partitioning Approach,” in Proceedings of the Fourth World Congress of Nonlinear Analysts (WCNA-04), Orlando, Florida, U.S.A., June 30 – July 7, 2004.
     [abstract] [pdf] [bibtex]
151. R. F. DeMara, A. Kejriwal, and J. R. Seeber, “Feedback Techniques for Dual-Rail Self-Timed Circuits,” in Proceedings of the 2004 International Conference on VLSI (VLSI-04), pp. 458-464, Las Vegas, Nevada, U.S.A., June 21-24, 2004.
     [abstract] [pdf] [ppt] [bibtex]
152. M. Georgiopoulos, J. Castro, E. Gelenbe, R. F. DeMara, A. J. Gonzalez, M. Kysilka, M. Mollaghasemi, and A. S. Wu, “CRCD Experiences at the University of Central Florida: An NSF Project,” in Proceedings of the 2004 American Society for Engineering Education Annual Conference and Exposition (ASEE-04), pp. 2432: 1-23, Salt Lake City, Utah, U.S.A., June 20-23, 2004.
     [abstract] [pdf] [bibtex]
153. J. Castro, M. Georgiopoulos, R. F. DeMara, and A. J. Gonzalez, “A Partitioned Fuzzy ARTMAP Implementation for Fast Processing of Large Databases on Sequential Machines,” in Proceedings of the Seventieth International Florida Artificial Intelligence Research Symposium (FLAIRS-04), Miami Beach, Florida, U.S.A., May 17-19, 2004.
     [abstract] [pdf] [bibtex]
154. J. C. Leon-Barth, R. F. DeMara, A. J. Gonzalez, and M. Georgiopoulos, “Bandwidth Optimizations for Integrated Tactical and Training Networks,” in Proceedings of the Second Swedish American Workshop on Modeling and Simulation (SAWMAS-04), pp. 24 -31, Cocoa Beach, Florida, U.S.A., February 1- 2, 2004.
     [abstract] [pdf] [bibtex]
155. J. J. Vargas, R. F. DeMara, A. J. Gonzalez, and M. Georgiopoulos, “Bandwidth Analysis of a Simulated Computer Network Executing OTB,” in Proceedings of the Second Swedish American Workshop on Modeling and Simulation (SAWMAS-04), pp. 201 – 208, Cocoa Beach, Florida, U.S.A., February 1 – 2, 2004.
     [abstract] [pdf] [bibtex]
156. M. Georgiopoulos, J. Castro, A. Wu, R. F. DeMara, E. Gelenbe, A. J. Gonzalez, M. Kysilka, and M. Mollaghasemi, “CRCD in Machine Learning at the University of Central Florida: Preliminary Experiences,” in Proceedings of the Eight Annual Conference on Innovation and Technology in Computer Science Education (ITiCSE-2003), pp. 249, Thessaloniki, Greece, June 30 -July 2, 2003.
     [abstract] [pdf] [bibtex]
157. M. Georgiopoulos, R. F. DeMara, E. Gelenbe, A. Gonzalez, M. Kysilka, M. Mollaghasemi, A. Wu, and I. Russell, “Machine Learning Advances for Engineering and Science Education: A CRCD Experience at the University of Central Florida”, in Proceedings of the Thirteenth International Conference on Artificial Neural Networks (ICANN-03), pp. 465-468, Istanbul, Turkey, June 26-29, 2003.
     [abstract] [pdf] [bibtex]
158. M. Georgiopoulos, I. Russell, J. Castro, A. Wu, M. Kysilka, R. F. DeMara, A. Gonzalez, E. Gelenbe, and M. Mollaghasemi, “A CRCD Experience: Integrating Machine Learning Concepts into Introductory Engineering and Science Programming Courses,” in Proceedings of the 2003 American Society for Engineering Education Annual Conference and Exposition (ASEE-03), pp. 1332: 1 -20, Nashville, Tennessee, U.S.A., June 22 -25, 2003.
     [abstract] [pdf] [bibtex]
159. J. D. Lohn, G. Larchev, and R. F. DeMara, “Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing,” in Proceedings of the Seventieth International Parallel and Distributed Processing Symposium (IPDPS-2003) Reconfigurable Architectures Workshop, pp. 172, Nice, France, April 22-26, 2003.
     [abstract] [pdf] [bibtex]
160. J. D. Lohn, G. Larchev, and R. F. DeMara, “A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs,” in Proceedings of the Fifth International Conference on Evolvable Systems (ICES-03), pp. 47-56, Trondheim, Norway, March 17-20, 2003.
     [abstract] [pdf] [bibtex]
161. J. Di, J. S. Yuan, and R. DeMara, “High Throughput Power-aware FIR Filter Design based on Fine-grain Pipeline Multipliers and Adders,” in Proceedings of the 2003 IEEE Annual Symposium on VLSI (ISVLSI-03), pp. 260-261, Tampa, Florida, U.S.A., February 20-21, 2003.
     [abstract] [pdf] [bibtex]
162. Y. Tseng and R. F. DeMara, “Communication Pattern based Methodology for Performance Analysis of Termination Detection Schemes,” in Proceedings of the Ninth International Conference on Parallel and Distributed Systems (ICPADS-02), pp. 535-541, Chungli Taoyuan, Taiwan, December 17-20, 2002.
     [abstract] [pdf] [bibtex]
163. J. D. Lohn and R. F. DeMara, “A Co-evolutionary Genetic Algorithm for Autonomous Fault-Handling in FPGAs,” in Proceedings of the Sixth International Conference on Military and Aerospace Programmable Logic Devices (MAPLD-2002), Laurel, Maryland, U.S.A., September 10-12, 2002.
     [abstract] [pdf] [bibtex]
164. A. E. Henninger, A. J. Gonzalez, M. Georgiopoulos, and R. F. DeMara, “A Connectionist-Symbolic Approach to Modeling Agents: Neural Networks Grouped by Contexts,” in Proceedings of the Third International and Interdisciplinary Conference on Modeling and Using Context (CONTEXT-01), pp. 198-209, Dundee Scotland, July 26-29, 2001.
     [abstract] [pdf] [bibtex]
165. A. E. Henninger, A. J. Gonzalez, M. Georgiopoulos, and R. F. DeMara, “Developing and Validating Human Behavioral Models through Learning By Observation,” in Proceedings of the 2001 World Multiconference on Systemics, Cybernetics and Informatics: Concepts and Applications (Part III), Orlando, FL, U.S.A., July 22-25, 2001.
     [abstract] [pdf] [bibtex]
166. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction,” in Proceedings of the 2001 International Workshop on Logic and Synthesis (IWLS-01), Granlibakken, California, U.S.A., pp. 185-189, June 12-15, 2001.
     [abstract] [pdf] [bibtex]
167. A. E. Henninger, A. J. Gonzalez, M. Georgiopoulos, and R. F. DeMara, “The Limitations of Static Performance Metrics for Dynamic Tasks Learned Through Observation,” in Proceedings of the Tenth Conference on Computer Generated Forces and Behavioral Representation (CGF-BR01), pp. 147-154, Norfolk, Virginia, U.S.A., May 14-17, 2001.
     [abstract] [pdf] [bibtex]
168. A. E. Henninger, A. J. Gonzalez, M. Georgiopoulos, and R. F. DeMara, “Human Performance Models for Embedded Training: A Novel Approach to Entity State Synchronization,” in Proceedings of the 2001 Advanced Simulation Technology Conference (ASTC-2001) Symposium on Military, Government, and Aerospace Simulation, Seattle, Washington, U.S.A., April 22-26, 2001.
     [abstract] [pdf] [bibtex]
169. A. E. Henninger, A. J. Gonzalez, W. Gerber, M. Georgiopoulos, and R. F. DeMara, “On the Fidelity of SAFs: Can Performance Data Help?” in Proceedings of the 2000 Interservice/Industry Training, Simulation and Education Conference (I/ITSEC-2000), pp. 147 -154, Orlando, Florida, U.S.A., November 27-30, 2000.
     [abstract] [pdf] [bibtex]
170. A. Gallagher, A. J. Gonzalez, and R. F. DeMara, “Modeling Platform Behaviors Under Degraded States Using Context-Based Reasoning,” in Proceedings of the 2000 Interservice/Industry Training, Simulation and Education Conference (I/ITSEC-2000), Orlando, Florida, U.S.A., November 27-30, 2000.
     [abstract] [pdf] [bibtex]
171. W. Kuang, J. S. Yuan, R. F. DeMara, D. Ferguson, and M. Hagedorn, “A Delay-insensitive FIR Filter for DSP Applications,” in Proceedings of the Ninth Annual NASA Symposium on VLSI Design, pp 2.2.1-2.2.7, Albuquerque, New Mexico, U.S.A., November 8-9, 2000.
     [abstract] [pdf] [bibtex]
172. N. Weng, J. S. Yuan, R. F. DeMara, D. Ferguson, and M. Hagedorn, “Glitch Power Reduction for Low Power IC Design,” in Proceedings of the Ninth Annual NASA Symposium on VLSI Design, pp. 7.5.1-7.5.7, Albuquerque, New Mexico, U.S.A., November 8-9, 2000.
     [abstract] [pdf] [bibtex]
173. A. E. Henninger, A. J. Gonzalez and M. Georgiopoulos, and R. F. DeMara, “Modeling Semi-Automated Forces with Neural Networks: Performance Improvement through a Modular Approach,” in Proceedings of the Ninth Conference on Computer Generated Forces and Behavioral Representation (CGF-BR00), Orlando, Florida, U.S.A., May 16-18, 2000.
     [abstract] [pdf] [bibtex]
174. B. S. Motlagh and R. F. DeMara, “A Scalable Replicated Concurrent-Read Architecture,” in Proceedings of the Fourteenth International Symposium on Computer and Information Sciences (ISCIS’99), Izmir, Turkey, October 18-20, 1999.
     [abstract] [pdf] [bibtex]
175. R. F. DeMara and P. J. Wilder, “A Taxonomy of High Performance Computer Architectures for Uniform Treatment of Multiprocessor Designs,” in Proceedings of the 1999 American Association for Engineering Education Southeastern (ASEE-SE99) Conference, pp. 1-9, Clemson, North Carolina, U.S.A., April 11-13, 1999.
     [abstract] [pdf] [bibtex]
176. A. E. Henninger, W. Gerber, R. F. DeMara, M. Georgiopoulos, and A. J. Gonzalez, “Behavior Modeling Framework for Embedded Simulation,” in Proceedings of the 1998 Interservice/Industry Training, Simulation and Education Conference (I/ITSEC-98), Orlando, Florida, U.S.A., November 30-December 3, 1998.
     [abstract] [pdf] [bibtex]
177. Y. Ma and R. F. DeMara, “Localized Knowledge Representation Scheme for Parallel Processing,” in Proceedings of the Fourth Joint Conference on Information Sciences (JCIS-98), pp. 81-86, Research Triangle Park, North Carolina, U.S.A., October 24-28, 1998.
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178. R. F. DeMara, H. Zhu, and M. Poston, “Rate Adaptive Source Quench Congestion Avoidance Techniques,” in Proceedings of the 1998 International Symposium on Information Theory and Applications (ISITA-98), pp. 572 -575, Mexico City, Mexico, October 14-16, 1998.
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179. A. J. Gonzalez, M. Georgiopoulos, R. F. DeMara, A. Henninger, and W. Gerber, “Automating the CGF Model Development and Refinement Process by Observing Expert Behavior in a Simulation,” in Proceedings of the Seventh Conference on Computer Generated Forces (CGF-98), Orlando, Florida, U.S.A., May 12-14, 1998.
     [abstract] [pdf] [bibtex]
180. B. S. Motlagh and R. F. DeMara, “Memory Latency in Distributed Shared-Memory Multiprocessors,” in Proceedings of the 1998 IEEE Southeastcon Conference (Southeastcon-98), pp. 134-137, Orlando, Florida, U.S.A., April 24-26, 1998.
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181. P. J. Wilder, R. F. DeMara, and M. Costello, “Formal Student Presentations: Two views on One Methodology,” in Proceedings of the 1998 American Association for Engineering Education Southeast Section (ASEE-SE-98) Conference, pp. 198-200, Orlando, Florida, U.S.A., April 5-7, 1998.
     [abstract] [pdf] [bibtex]
182. A. J. Gonzalez, R. F. DeMara, and M. Georgiopoulos, “Vehicle Model Generation and Optimization for Embedded Simulation,” in Proceedings of the 1998 Spring Simulation Interoperability Workshop (SIW-98), Orlando, Florida, U.S.A., March 9-13, 1998.
     [abstract] [pdf] [bibtex]
183. H. Bahr, R. F. DeMara, and M. Georgiopoulos, “Integer-Encoded Massively Parallel Processing of Fast-Learning ARTMAP Networks,” in Proceedings of the 1997 SPIE AeroSense Symposium (AeroSense-97), pp. 678 – 689, Orlando, Florida, U.S.A., April 21 – 24, 1997.
     [abstract] [pdf] [bibtex]
184. H. Bahr and R. F. DeMara, “A Concurrent Model Approach to Scaleable Distributed Interactive Simulation,” in Proceedings of the Fifteenth Workshop on the Interoperability of Distributed Interactive Simulation, pp. 215-222, Orlando, Florida, U.S.A., September 16 – 20, 1996.
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185. S. E. Crawford and R. F. DeMara, “Cache coherence in a multiport memory environment,” in Proceedings of the Second International Conference on Massively Parallel Computing Systems (MPCS-95), pp. 632-642, Ischia, Italy, May 2-6, 1995.
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186. R. F. DeMara, B. S. Motlagh, E. Lin, and S. Kuo, “Barrier Synchronization Techniques for Distributed Process Creation,” in Proceedings of the Eighth International Symposium on Parallel Processing (IPPS-94), pp. 597 – 603, Cancun, Mexico, April 26 – 29, 1994.
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187. R. N. Mercer, M. Ebel, and R. F. DeMara, “Pipelined Architecture for Computational Nanotechnology,” in Proceedings of the 1994 IEEE Southcon Conference (Southcon-94), pp. 314 – 319, Orlando, Florida, U.S.A., March 29 – 31, 1994.
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188. R. A. Cagle, R. B. Holl, and R. F. DeMara, “Multifunction Content Addressable Memory for Parallel Speech Understanding, in Proceedings of the 1994 IEEE Southcon Conference (Southcon-94), pp. 320 -325, Orlando, Florida, U.S.A., March 29 – 31, 1994.
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189. R. Mercer, M. Ebel, and R. F. DeMara, “Helical Boolean Logic Elements,” in Proceedings of the Third Foresight Conference on Molecular Nanotechnology, Palo Alto, California, U.S.A., October 14 – 16, 1993.
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190. J. D. Roberts, R. F. DeMara, G. Ellis, R. Hughey, R. Levinson, and C. Noshpitz, “AHP: Advanced Hardware for PIERCE, in Proceedings of the Second International Workshop on PIERCE, pp. 26-29, Quebec, Canada, August 7, 1993.
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191. S. H. Chung, R. F. DeMara, and D. I. Moldovan, “PASS: a parallel speech understanding system,” in Proceedings of the Ninth IEEE Conference on AI for Applications (CAIA-93), pp. 136-142, Orlando, Florida, U.S.A., March 1-5, 1993.
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192. R. F. DeMara and H. Kitano, “Benchmarking Performance of Massively Parallel AI Architectures,” in Proceedings of the Fourth Symposium on the Frontiers of Massively Parallel Computation, pp. 517-520, McLean, Virginia, U.S.A., October 19-21, 1992.
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193. R. F. DeMara and D. I. Moldovan, “Marker-Passing on a Parallel Knowledge Processing Testbed, in Proceedings of the First International Conference on Parallel and Distributed Information Systems (PDIS-91), pp. 180, Miami, Florida, U.S.A., December 4 – 6, 1991.
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194. R. F. DeMara and H. Kitano, “PACE Benchmark Set,” in Proceedings of the 1991 International Joint Conference on Artificial Intelligence (IJCAI 91) Workshop on Parallel Processing for AI, pp. 517 -520, Sydney, Australia, August 24 – 25, 1991.
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195. R. F. DeMara and D. I. Moldovan, “Performance Indices for Parallel Marker-Propagation,” in Proceedings of the 1991 International Conference on Parallel Processing (ICPP-91), pp. 658 -659, St. Charles, Illinois, U.S.A., August 12 – 16, 1991.
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196. R. F. DeMara and D. I. Moldovan, “A DSP Architecture for Parallel AI Processing,” in Proceedings of the 1991 TMS320 Educators Conference, Houston, Texas, U.S.A., July 31-August 2, 1991.
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197. R. F. DeMara and D. I. Moldovan, “The SNAP-1 Parallel AI Prototype,” in Proceedings of the Eighteenth Annual International Symposium on Computer Architecture (ISCA-91), pp. 2 – 11, Toronto, Ontario, Canada, May 27 – 30, 1991. Also appears in Computer Architecture News, Vol. 19, No. 3, pp. 2 – 11, May, 1991.
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198. R. F. DeMara and D. I. Moldovan, “Design of a Clustered Multiprocessor for Real-time Natural Language Understanding, in Proceedings of the Fifth International Parallel Processing Symposium (IPPS-91), pp. 270-277, Anaheim, California, U.S.A., April 30-May 2, 1991.
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199. R. F. DeMara, “Characterizing Marker-Propagation Mechanisms,” in Proceedings of the First Workshop on Abstract Machine Models for Highly Parallel Computers, pp. 77-82, Leeds, United Kingdom, March 25 – 27, 1991.
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